Pulsed-plasma chemical vapor deposition was used to deposit thin films from four different organosilicon (OSG) precursors, using water as the oxidant. The OSG precursors varied in structure (cyclic or acyclic), chemical composition (siloxane or silane), and type of organic substituent. Significant differences in final film structure were observed based on precursor identity, with the primary result being that cyclic siloxane precursors yielded films with a greater degree of crosslinking. The identity of the organic substituents was shown to affect the crosslinking potential, in that more reactive side groups, such as vinyl groups, facilitated the formation of crosslinking groups. At low power (200 W), film structure was dictated by precursor identity, whereas at high power (400 W), film structure became more uniform and precursor identity was less important. Mechanical properties tracked with plasma power, with low power samples being relatively soft, with hardness values between 0.126 GPa and 0.536 GPa. Samples produced at higher powers are more extensively crosslinked, resulting in enhanced mechanical properties. Samples produced at high powers had hardness values between 0.679 and 3.22 GPa, depending upon precursor identity. Dielectric constants ranged between 2.3 and 4.0.

A plasma-enhanced atomic layer deposition (PEALD) process for the growth of tantalumbased compounds is employed in integration studies for advanced copper metallization on a 200- mm wafer cluster tool platform. This process employs terbutylimido tris(diethylamido)tantalum (TBTDET) as precursor and hydrogen plasma as the reducing agent at a temperature of 250°C. Auger electron spectrometry, X-ray photoelectron spectrometry, and X-ray diffraction analyses indicate that the deposited films are carbide rich, and possess electrical resistivity as low as 250νΔcm, significantly lower than that of tantalum nitride deposited by conventional ALD or CVD using TBTDET and ammonia. PEALD Ta(C)N also possesses a strong resistance to oxidation, and possesses diffusion barrier properties superior to those of thermally grown TaN.

A process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

An ion-assisted chemical vapor deposition method by which Cu is deposited preferentially from the bottom of trenches (anisotropic CVD) has been proposed in order to fill small via holes and trenches. By using Ar + H2 + C2H5OH[Cu(hfac)2] discharges with a ratio H2 / (H2 + Ar) = 83%, Cu is filled preferentially from the bottom of trenches without deposition on the sidewall and top surfaces. The deposition rate on the bottom surface of trenches is experimentally found to increase with decreasing its width.

The current challenge in designing new low-k dielectrics is realizing sufficient mechanical and chemical stability such that the material can be integrated into current damascene schemes. The material of interest in this study is a nonporous SiCOH composite (carbon-doped silicon oxide, also known as organosilicate glass “OSG”) for use as an intermetal dielectric (IMD). During integration of this IMD, processing steps such as etch, resist strip and chemicalmechanical polishing for planarization may chemically alter the outer layer of the dielectric. Here, spectroscopic ellipsometry is used to characterize the modified layer of SiCOH films after exposure to different resist strip plasmas. The data are analyzed based on a 2-layer model, consisting of a carbon-deficient layer on the surface of the low-k SiCOH dielectric. This model is supported by XPS and FTIR data. The effects of two types of plasma etch chemistry on the formation of this modified layer were studied, and differences between the two chemistries were found. The 2-layer model accurately describes the modifications produced by the oxidizing plasma, but its description of the modified layer formed by the plasma involving nitrogen is not complete. A 3-layer model with an additional nitrogen-doped layer is suggested.

A three-step baseline process for thinning of bonded wafers for applications in threedimensional (3D) integration is presented. The Si substrate of top bonded wafer is uniformly thinned to ~35 μm by backside grinding and polishing, followed by wet-etching using TMAH. No visible changes at the bonding interface and damage-free interconnect structures are observed after the thinning process. Both mechanical and electrical integrity of the bonded pairs are maintained after the three-step baseline thinning process, with electrical tests on wafers with multi-level copper interconnect test structures showing only a slight change after bonding and thinning. This thinning process works well for Si removal to an etch-stop layer, although present process uniformity is not adequate to thin bulk Si substrates. Other issues such as wafer breakage and edge chipping during Si thinning and their possible solutions are also addressed.

The thermomechanical reliability of Cu/low-k interconnects, which is directly related to yield problems and premature device failures, has been a major issue. The development of a manufacturing process, which can satisfy the most stringent reliability standards, requires detailed information on the thermomechanical behavior of Cu/low-k interconnects. The thermomechanical behavior of Cu/low-k interconnects is complicated by the fact that processinduced thermal stresses are developed during the manufacturing process. A conventional finite element analysis (FEA) approach has some difficulties to model Cu/low-k interconnects that keep changing during process steps. Therefore, a sequential process modeling technique has been developed to simulate the interconnect behavior to substantially any level of detail and understand the complex thermomechanical behavior of Cu/low-k interconnects while being manufactured. In this paper, we briefly describe a sequential process modeling technique and demonstrate how we use the modeling technique to solve a Cu/SiC delamination problem in a Cu/SiLK* semiconductor dielectric dual damascene test structure.

Test wafers were prepared under different process conditions of barrier and seed film deposition, in order to study the effects on tungsten plug filling. Tungsten fill percentage was measured using laser-induced surface acoustic wave metrology on plug arrays of varying plug diameter and the results were verified by SEM cross-section. The data show that, for via diameters of 0.12 micron or less, the seed deposition process is a critical factor in effective (void free) plug filling. Seed deposition by ALD and low-temperature CVD were found to be far more effective than conventional CVD. Changing the thickness of the TiN barrier layer was found to have minimal effect on the occurrence of voids. For via diameters greater than 0.12 microns, all of the seed processes led to relatively little voiding.

Defect spectrum N(E) of porous organic dielectric (POD) films is studied with capacitance deep-level-transient-spectroscopy (C-DLTS) in the energy range up to 0.7 eV below conduction band bottom Ec. The POD films were prepared by spin coating onto 200mm p-type (1 – 10 Δcm) single-side polished silicon substrates followed by baking at 325°C on a hot plate and curing at 425°C in furnace. The film thickness is in the 5000 – 6000 Å range. The ‘sandwich’ -type NiCr/POD/p-Si/NiCr test structures showed both rectifying DC current-voltage characteristics and linear 1/C2 vs. DC reverse bias voltage. These confirm the applicability of the C-DLTS technique for defect spectrum deconvolution and the n-type conductivity of the studied films. Isochronal annealing (30 min in argon or 60 min in nitrogen) has been performed over the temperature range 300°C - 650°C. The N(E) distribution is only slightly affected by annealing in argon. However, the distribution depends strongly on the annealing temperature in nitrogen ambient. A strong N(E) peak at Ec – E = 0.55 – 0.60 eV is detected in all samples annealed in argon but this peak is practically absent in samples annealed in nitrogen at Ta < 480°C. On the other hand, two new peaks at Ec – E = 0.12 and 0.20 eV appear in the N(E) spectrum of the samples annealed in nitrogen at Ta = 650°C. The different features of the defect spectrum are attributed to different interactions of argon and nitrogen with dangling carbon bonds on the intra-pore surfaces.

The physics and mechanics of a fracture toughness measurement technique for low-k films are described. It has been observed experimentally that it is possible to generate reproducible stable cracks at indentation sites in thin low-k films using cube-corner indentation. The fracture response depends on the film thickness and follows no simple scaling laws. The physics of a model that takes into account the stress fields from indentation and film stress, with particular attention paid to the Poisson's ratio of the film, are described. The model is able to predict the changes in observables when the film thickness is changed, which allows one to estimate film toughness independent of the configuration of the material.

A trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Porous SiLK resin is an ultra-low-k interlayer dielectric (ILD) material designed to meet the needs of the 65 nm technology node and beyond. In early 2002, the porous SiLK resin formulation was defined and scaled up, facilitating the tight monitoring and control of key properties, including pore size distribution, over several lots of material. The film processing kinetics are now well understood and a wide process window exists which ensures optimum pore morphology and pore size distribution. Thermal cycling of films demonstrates no effect on pore morphology or dielectric constant. The material has been designed to minimize the impact of CTE mismatch at high temperature, which challenged the integration of some previous generations of SiLK and porous SiLK dielectric resins. The discrete, closed-cell pore geometry is well characterized and enables the extendibility of process module development from SiLK resin technology to porous SiLK resin. Concurrent with the scale up efforts, advancements in minimizing both cure time and temperature simultaneously, as well as significant improvements in pore size and pore size distribution, have been achieved. The cure and porogen burn out time has been reduced by 50% or greater, and the temperature has been reduced to 370°C. The pore size has been reduced by ∼35%, and the pore size distribution has been narrowed by ∼40%. These advancements have resulted in the introduction of porous SiLK T resin, with a dielectric constant of k = 2.4 and a recommended cure temperature of 370°C, and the introduction of porous SiLK U resin, with a mean pore diameter of ∼5 nm and a dielectric constant of k = 2.2.

A nondestructive methodology for characterizing Cu interconnects in integrated circuits (ICs) has long been sought and has motivated significant efforts regarding metrology tool development. Here, we present investigations of high-frequency heterodyne force microscopy (HFM) to investigate the acoustic response of damascene-processed Cu interconnects in a silicon oxide dielectric. HFM is a phase-resolved mechanical imaging technique that can, in principle, measure acoustic phase variations with nanometer spatial resolution. HFM measurements at carrier frequencies of 10.8 MHz and 72.5 MHz reveal phase differences of 0.5°-0.7° and 3.5°-4.5°, respectively, between the SiO2 and Cu regions of the IC test structure. Such phase differences are consistent with expected variations due to acoustic propagation time differentials between the Cu and SiO2 regions. Coupled with detailed mechanical measurements of the Cu and SiO2 regions this data may be used to extract spatial maps of acoustic phase delay and investigate subsurface features of similar IC test structures.

The annealing of Ag(40 at.% Cu) alloy films deposited on a Si substrate at 200 – 800 oC in vacuum has been conducted to investigate the formation of Cu3Si at the Ag-Si interface and its effects on adhesion and resistivity of Ag(Cu)/Si structure. Auger electron spectroscopy(AES) analysis showed that annealing at 200°C allowed a diffusion of Cu to the Si surface, leading to the significant reduction in Cu concentration in Ag(Cu) film and thus causing a rapid drop in resistivity. In addition, the segregated Cu to the Si surface reacts with Si, forming a continuous copper silicide at the Ag(Cu)/Si interface, which can contribute to an enhanced adhesion of Ag(Cu)/Si annealed at 200 oC. However, as the temperature increases above 300°C, the adhesion tends to decrease, which may be attributed to the agglomeration of copper silicide beginning at around 300°C.

Normal photolithography tools have focal depth limitations and are unable to meet the expectations of high resolution photolithography on highly topographic structures. This paper shows a cost effective and promising technique of combining two different approaches to achieve critical dimensions of traces on slope pattern continuity on highly topographic structures. Electrophoretically deposited photoresist is used on 3-D structured wafers. This photoresist coating technique is fairly known in the MEMS industries to achieve uniform and conformal photoresist films on 3D surfaces. Multi step exposures are used to expose electrophoretically deposited photoresist. AlCu (Cu-0.5%), 0.47-0.53 μm thick metal film is deposited on 3D structured silicon substrate to plate photoresist. By combining these two novel methods, metal (AlCu) traces of 75 μm line width and 150 μm pitch (from top flat to down the slope) have been demonstrated on isotropically etched 350 μm deep trenches with 5-10% line width loss.

Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport is dominated by diffusion at the Cu/SiNx cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM. For all the ILDs studied, (jL)c showed no temperature dependence.

The conventionally used sequence for copper damascene metallization consists of barrier deposition, physical vapor deposition (PVD) Cu seed and electroplated copper. Due to the limited step coverage of PVD copper, the extendibility of this sequence to feature dimensions below 90 nm is at risk. To reduce the risk of pinch-off of very small features, the PVD layer thickness will be reduced well below 100 nm, the drawback being poor seed coverage at the bottom of the features. Void free fill by electroplating is hence at risk by both pinch-off and discontinuous seed coverage (3-5). In this paper, the use of a conformal metal deposition method, electroless copper, to enhance PVD seed layers as thin as 10 nm is presented. It is demonstrated that sparse, discontinuous copper films provide a catalytic surface for electroless copper deposition. With electroless copper, void-free copper fill of 12.5 aspect ratio (AR) trenches (70 nm width) and 8.3 AR vias is achieved. Furthermore, 6 nm thin electroless copper films were integrated in a dual damascene process and electrically characterized. A yield of approximately 85% was achieved on via chains (360000 links, 0.25 by 1.1 μm vias), with 10 nm PVD seed. This was comparable to the yield when using 100 nm PVD seed. Hydrogen, generated as a byproduct during the electroless copper ion reduction, was found in the copper deposits as well as in the barrier films underneath. In some cases, spontaneous blistering in the plated copper film was observed, and is believed to be due to hydrogen incorporation. The interaction of electroless copper films with various barrier materials (PVD Ta, PVD TaN, CVD TiN(Si) and combinations) is discussed. Electromigration test results presented in this paper indicate that the failure mechanism is not qualitatively different from reference samples with the conventional PVD seed.

Small-angle neutron scattering (SANS) contrast variation is used to characterize matrix properties and pore size in nanoporous low-dielectric constant (low-k) thin films. Using a vapor adsorption technique, SANS measurements are used to identify a “contrast match” solvent mixture containing the hydrogen– and deuterium-containing versions of a probe solvent. The contrast match solvent is subsequently used to conduct SANS porosimetry experiments. With information from specular X-ray reflectivity and ion scattering, the technique is useful for estimating the mass density of the matrix (wall) material and the pore size distribution. To illustrate the technique, a porous methylsilsesquioxane (MSQ) spin-on dielectric is characterized.

Dry etching of Cu challenges the Focused Ion Beam (FIB) removal of metallizations. Cu metallizations are comprised of numerous, randomly orientated crystallites. Each orientation shows a different etch rate under ion bombardment, leading to unacceptable damage to underlying dielectric. An improved methodology for uniform Cu etching over dielectric consists of three steps: 1) Exposure, 2) Initial off-normal bombardment and 3) Chemistry assisted ion bombardment. Comparison is made with and without preliminary off-normal bombardment. It is shown that Cu etching preceded by off-normal bombardment was completed ∼50% sooner with decreased dielectric over-etch.

In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called “wiring crisis”), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.

The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.