The breakdown of ultra-thin gate oxide layers is investigated using fast-feedback Hg-probe measurements to perform Exponentially Ramped Current Stress (ERCS) tests. Several parameters have been varied in the ERCS test: oxide thickness (4nm, 5nm, 6nm and 7nm), capacitor area (0.12cm2 and 0.023cm2) and initial injected current (5×10−5 A and 5×10−4 A). Soft breakdown is detected only in case of oxides thinner than 5 nm. It is found that the fraction of points on the wafer on which soft breakdown occurs reduces by increasing the value of the injected current at the beginning of the ERCS test or completely disappears by decreasing the capacitor area. Consequences of current results for correct routine assessment of gate oxide integrity in microelectronic manufacturing are discussed.

An understanding of dielectric breakdown mechanisms is critical for continued oxide scaling. Although working transistors have been demonstrated with sub-2nm SiO2 gate dielectrics, the manufacturability of such devices hinges on the reliability of the oxide. As oxides become thinner and operating voltages become lower, a fundamentally different mode of dielectric breakdown occurs. This has been called soft breakdown and is considered to be the formation of a small, localized tunneling path through a dielectric. For transistors with 2-nm gate oxides, threshold voltage and maximum transconductance are not affected by soft breakdown, implying that circuits may continue to operate after soft breakdown. The increase in gate current or voltage noise associated with soft breakdown is not a limiting factor for many applications. However, some cases will be shown in which soft breakdown does degrade device function.

In order to make comparisons of ultra-thin oxide quality, it is important to be able to reliably detect soft breakdown. J-ramp, a commonly used ramped-current measurement to determine oxide quality, is unable to detect soft breakdown in ultra-thin oxides. We will demonstrate the incorporation of noise measurements in a commercial J-ramp algorithm.

The time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

Breakdown characteristics of ultra-thin gate oxides caused by plasma charging were studied in this work. It is observed that as oxide thickness is scaled down to 4 nm, some traditional monitor parameters may lose their sensitivity for detecting oxide degradation induced by plasma charging damage, due to insignificant trap generation. Even the gate leakage current, although sensitive for 4 nm oxide, may no longer be sensitive enough for even thinner oxide (e.g., 2.6 nm), due to the existence of large tunneling current. Moreover, several soft-breakdown events were found to occur in ultrathin oxide before the final onset of a catastrophic hard-breakdown. Finally, an equivalent local oxide thickness is calculated using local oxide thinning model to estimate the stepwise increase of gate current after soft-breakdown event.

A design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.

A remote plasma enhanced-metal organic chemical vapor deposition (RPE-MOCVD) process was developed for the preparation of non-crystalline (ZrO2)x-(SiO2)1−x (x ≤ 0.5) alloys, targeting the compound composition ZrSiO4with k ∼ 12.5. Shifts in Si LVV and Zr LMM AES energies with respect to elemental values showed that the deposited film was a fully-oxidized zirconium/silicon alloy. FTIR results were consistent with AES, and a Zr-O-Si bonding mode was identified in the spectra. The films were amorphous before and after RTA at 900°C for 30 sec, as monitored via RHEED. Optical absorption measurements indicated the onset of band-to-band transitions at an energy of approximately 6 eV. Finally, C-V testing showed that the films were insulating.

A side-by-side comparison of the TiO2 deposition kinetics and the corresponding film microstructures using titanium(IV) isopropoxide and anhydrous titanium(IV) nitrate was conducted at low pressures (< 10−4 Torr) in an ultrahigh vacuum chemical vapor deposition reactor. Titanium(IV) nitrate exhibited a lower activation energy of reaction (Er= 98 kJ/mol) which allowed deposition at lower temperatures compared to titanium(IV) isopropoxide (Er= 135 kJ/mol). Comparison of the microstructures of films deposited at similar temperatures revealed significant differences in the reaction rate limited kinetic regime. As the growth rates of the two precursors converged in the flux-limited regime, the respective microstructures became indistinguishable.

We investigated the use of TiO2 as an alternate gate dielectric for future CMOS applications. To reduce the leakage current, different post deposition treatments were investigated. It was found that for very thin TiO2 films, ozone plasma exposure is an effective way in lowering thermal budget of the post deposition annealing. Doping TiO2with Si and/or Al can also be effective in substantially reducing the leakage current. In addition, the doped TiO2 has the desirable property of remaining amorphous even after anneal at 850°C. We also report the fabrication of submicron MOSFETs with TiO2 gate dielectrics equivalent to 2 nm of SiO2 and TiN/Cu gate electrodes.

Ultrathin tantalum pent-oxide (Ta2O5) films with a high dielectric constant over 20 and which are thinner than 10 nm have been extensively studied to realize small area capacitors for memories and high performance MOSFETs. The author and his colleagues started working on ultrathin Ta2O5 films with an equivalent oxide film thickness less than 4 nm for small capacitors for bipolar memories and DRAMS in 1984, and investigated extensively the effects of dry oxygen annealing of sputter-deposited thin Ta2O5 films on Si. We found that there was a process window (dry O2, 800 °C) where defects causing initial and latent breakdown were significantly reduced and where at the same time the reduction in the capacitance inevitably caused by the growth of interfacial SiO2 is kept small. This dry O2 annealing has been widely used for many years due to its effectiveness. This treatment was called “weak spot oxidation.” The interfacial SiO2, with a smaller dielectric constant of 3.9, underneath the Ta2O5 films causes a reduction of the capacitance and an increase of the equivalent film thickness. Annealing of the films after deposition and suppression of the interfacial SiO2 growth are the keys to realizing high performance and reliable Ta2O5 capacitors and gate insulators. In this paper, these fundamental processes are described, along with more recent developments of Ta2O5 thin film technologies, and the potential of the Ta2O5 films as an alternative for a future ULSI gate insulator are also discussed.

In this work we report on tantalum oxide fabricated by anodic oxidation of tantalum nitride and tantalum silicide to be used as the dielectric of Metal-Insulator-Metal (MIM) capacitors. These films exhibit greatly improved leakage currents, breakdown voltage and very low defect density, thus allowing the fabrication of large area capacitors. Several counter and bottom electrodes have been used and compared. The effects of the different processing conditions (top-electrode metals, annealing conditions, bottom electrode stoichiometry and precursor) on the capacitor performances are extensively discussed throughout this work. The electrical behavior of the resulting high-density MIM capacitors has been extensively characterized. Finally, we propose a set of selection guides to select the more appropriate process parameter values and electrode materials for a given application of these capacitors.

Tantalum pentoxide (Ta2O5) films were formed by oxidizing thin tantalum (Ta) films on bare and NO-nitrided silicon substrates. The 43-400 Å thick Ta films were deposited using physical vapor deposition (PVD) and oxidized using O2 for 2-60 min at 550-800 C in a furnace or single wafer tool. Uniform and stoichiometric Ta2O5 films were successfully produced as determined from XRD, AES depth profiling, XTEM, and ellipsometric analysis. The nitridation pretreatment was found to minimize the interfacial Ta-Si reactions which occur during the oxidation. Well-behaved CV and IV curves were obtained from mercury probe measurements. No CV hysteresis was observed. An equivalent oxide thickness of 38 Å and a leakage current of 7×10−9 A/cm2 at +1V were obtained for a 120 Å thick Ta2O5 film on a 15 Å interfacial SiO2 layer.

In this paper, ultra thin CVD Ta2O5 stacked gate dielectrics (Teq∼14Å-22Å) was fabricated by in-situ RTP processing. The leakage current of Ta2O5 devices is 103× lower leakage current compared to SiO2 of identical thickness for devices with Teq between 18Å-22Å. While Teq<18Å, the leakage current follows same train and J∼10−3A/cm2 for Ta2O5 stacked gate dielectrics with Teq=14Å. Superior interface properties and reliability have been obtained.

Gate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.

In this paper the new technique of ultraviolet-assisted injection liquid source (UVILS) chemical vapour deposition (CVD) of thin tantalum pentoxide films on p-type Si (100) wafers is presented. This method involves the use of a krypton chloride (KrCl*) excimer lamp, radiating at 222 nm, and a novel injection liquid source capable of delivering precisely controllable quantities of a novel high-volatility liquid metalorganic precursor into the CVD chamber. The physical and chemical properties of the films formed have been studied using spectroscopic ellipsometry and Fourier transform infrared spectroscopy measurements while the electrical properties of the films were determined by surface charge analysis, capacitancevoltage, and current-voltage measurements. Simple metal/oxide/silicon capacitor structures incorporating this tantalum pentoxide have been fabricated. Refractive index values of 2.09±0.07, dielectric constant values of 18-24, fixed oxide charge content of < 1 × 1011 cm−2 and breakdown fields higher than 2 MV/cm can be readily obtained in the as-deposited films.

A major hurdle in the gate dielectric scaling using conventionally grown SiO2 has been excessive tunneling that occurs in ultra-thin (<25Å) SiO2. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta2O5 interface trap states, and low Silicon interface carrier mobilities. Stacked Ta2O5 gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first SiO2 (8-12Å) layer of the SiO2-Ta2O5 stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness (Tox) of these oxides measured by COS indicates this hydrocarbon layer has no impact on Tox. Stacked Ta2O5 was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick Ta2O5 layer at 480°C, 300mTorr followed by an in-situ 550°C UV-03 anneal to densify the Ta2O5 film and grow an additional 5Å SiO2 layer underneath the first grown SiO2 layer resulting in an effective SiO2 thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown SiO2 layer resulting in an effective SiO2 thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements.

High K (dielectric constant) and silicon-compatibility are essential for an alternative gate dielectric for use in silicon MOSFETs. Thermodynamic data were used to comprehensively evaluate the thermodynamic stability of binary oxides and binary nitrides in contact with silicon at 1000 K. Using the Clausius-Mossotti equation and ionic polarizabilities, the K of all known inorganic compounds composed of Si-compatible binary oxides was estimated. A ranked list of alternate gate oxide candidates that are likely to possess both high K and silicon-compatibility is given.

Since the advent of the integrated circuit in 1959 and the introduction of MOS capacitors in the early ‘60’s, electronic technology has relied on silica (SiO2) as the gate dielectric in a field effect transistor. However, silica-based transistor technology is approaching fundamental limits. Feature-size-reduction and the ever-demanding technology roadmaps have imposed scaling constraints on gate oxide thickness to the point where excessive tunneling currents make transistor design untenable; an alternative gate dielectric is needed. Crystalline oxides on silicon (COS), simply by virtue of their high dielectric constants, could fundamentally change the scaling laws for silicon-based transistor technology. More importantly, COS could provide the opportunity for an entirely new device physics based on anisotropic response of crystalline oxides grown commensurately on a semiconductor. In this paper, we report that high dielectric constant alkaline earth and perovskite oxides can be grown in perfect registry with silicon. Commensurate heteroepitaxy between the semiconductor and the oxide is established via a sequenced transition that uniquely addresses the thermodynamics of a layer-by-layer energy minimization at the interface. The perfection of the physical structure couples directly to the electrical structure, and we thus obtain the unparalleled result of an equivalent oxide thickness of less than I nm in a MOS capacitor. With this demonstration it is apparent that COS presents a functional alternative to SiO2. With COS, a transistor gate can not only exhibit a much higher dielectric response, but add entirely new capabilities such as logic-state retention with the anisotropic response of ferroelectric polarization in a ferro-gated device. COS is the basis for fundamental change in semiconductor technology.

Single crystalline perovskite oxides such as SrTiO3 (STO) are highly desirable for future generation ULSI applications. Over the past three decades, development of crystalline oxides on silicon has been a great technological challenge as an amorphous silicon oxide layer forms readily on the Si surface when exposed to oxygen preventing the intended oxide heteroepitaxy on Si substrate. Recently, we have successfully grown epitaxial STO thin films on Si(001) surface by using molecular beam epitaxy (MBE) method. Properties of the STO films on Si have been characterized using a variety of techniques including in-situ reflection high energy electron diffraction (RHEED), ex-situ X-ray diffraction (XRD), spectroscopic ellipsometry (SE), Auger electron spectroscopy (AES) and atomic force microscopy (AFM). The STO films grown on Si(001) substrate show bright and streaky RHEED patterns indicating coherent two-dimensional epitaxial oxide film growth with its unit cell rotated 450 with respect to the underlying Si unit cell. RHEED and XRD data confirm the single crystalline nature and (001) orientation of the STO films. An X-ray pole figure indicates the in-plane orientation relationship as STO[100]//Si[110] and STO(001)// Si(001). The STO surface is atomically smooth with AFM rms roughness of 1.2 AÅ. The leakage current density is measured to be in the low 10−9 A/cm2 range at 1 V, after a brief post-growth anneal in O2. An interface state density Dit = 4.6 × 1011 eV−1 cm−2 is inferred from the high-frequency and quasi-static C-V characteristics. The effective oxide thickness for a 200 Å STO film is around 30 Å and is not sensitive to post-growth anneal in O2 at 500-700°C. These STO films are also robust against forming gas anneal. Finally, STO MOSFET structures have been fabricated and tested. An extrinsic carrier mobility value of 66 cm2 V−11 s−1 is obtained for an STO PMOS device with a 2 μm effective gate length.

The electronic properties of oxides that are candidates for high-dielectric insulators in ULSI are discussed. The theoretical models that can be used to describe them are compared, and the properties of cation oxidation state and point defects associated with non-stoichiometry in the bulk and on the surface are considered. Metal-oxide surfaces often reconstruct, with the creation of a surface dipole moment The effect of overlayers on metal-oxide surfaces is also discussed.

In this article, the properties of plasma deposited Al2O3 and Ta2O5 thin films (k ≈ 12 and 25 respectively) are discussed as possible high k alternatives to SiO2. The films were formed in a 4” compatible triode plasma CVD reactor using Ta(V)ethoxide for Ta2O5 and Al acetylacetonate, Al tri-sec-butoxide, Al triisopropoxide, and triethyldialuminum tri-sec-butoxide metal organic precursors for Al2O3. Precursors were heated to 150 °C and delivered to the reactor with He and Ar carrier gases downstream from the plasma. For Ta2O5 films, film properties were strongly dependent on the oxygen precursor, with O2 resulting in higher growth rates, better uniformity, and better stability to water exposure than films deposited using N2O. For Al2O3, distinct differences in OH and C incorporation were observed for the various Al and O precursors studied. In particular, films deposited from alkoxides had higher concentrations of OH and C, and had higher leakage currents. For films deposited with triethydialuminum tri-sec-butoxide, the N2O plasma O atom source resulted in smaller leakage currents and less C than an O2 plasma. Temperature dependence of the deposition rates and the leakage currents was also observed.