The MESC/CTMC compatible, Advance 2500 cluster tool made by ASM is evaluated for the manufacturing of CMOS gate stack structures based on CVD silicon nitride rather than thermally grown silicon oxide as the gate dielectric material, and polysilicon as the gate electrode material. With two different CVD chemistries excellent growth characteristics and thickness uniformity control of the silicon nitride is demonstrated. Electrical assessment reveals lower leakage current as compared to silicon oxide and minimal hysteresis in C-V curves, even for gates stacks that have an equivalent oxide thickness below 1.5nm. The best properties are for silicon nitride films that also have a low H2 content.

This is to report the feasibility of ultra-thin silicon nitride (SiNx) films, prepared by catalytic chemical vapor deposition (Cat-CVD) method, as an ultra-thin gate insulator. In the Cat-CVD method, the deposition gases such as a gaseous mixture of silane (SiH4) and ammonia (NH 3) are decomposed by catalytic cracking reactions with a heated tungsten catalyzer placed near substrates, and SiNx films are formed at substrate temperatures around 300°C without using plasma. In the paper, additionally the effect of post-deposited treatments by using NH3-decomposed species or hydrogen (H2)-decomposed species formed by catalytic cracking of NH3 and H2 are also studied. It is found that a small hysteresis loop is seen in the C-V curve of as-deposited Cat-CVD SiNx films and that the leakage currents with thickness of 3nm equivalent oxide thickness (EOT) is slightly larger than that in the conventional thermal SiO2 of similar EOT. However, it is also found that the properties of Cat-CVD SiNx films are drastically improved by the post-deposited H2 or NH3 treatments, that is, the hysteresis loop disappears and the leakage current decreases by three orders of magnitude.

The atomic-scale surface roughness of ultrathin thermal oxides formed on Si(100) were studied as a function of oxide film thickness up to the thickness of 2.0 nm. The height deviation on oxide surface is limited within single atomic-step height of 0.135 nm on Si(100) surface below the oxide film thickness of about 1 nm, but above this thickness the height deviation increases with the increase in thickness at 700°C. This increase in height deviation with thickness must be produced by the relaxation of oxidation–induced stress in bulk SiO2. Furthermore, the oscillation in surface roughness with constant amplitude and its oscillating period in oxide film thickness of 0.19 nm were found.

We report the first direct observation of dissociative chemisorption of oxygen molecules on a silicon surface at room temperature via a molecular precursor state. We link this to the fact that smooth oxide layers can be grown easily on Si(113). The process of initial oxidation is discussed in terms of surface diffusion paths and surface stress. First ab initiocalculations help elucidate the favored adsorption sites and the oxidation mechanism. Experimental evidence was found for bond geometries resulting in the quasi-epitaxial growth of a chemisorption layer on the substrate at elevated temperatures (600°C). In contrast to the first stages of Si(001) oxidation, neither defects nor the ejection of Si atoms plays a significant role during the initial oxidation of Si(113).

In this paper, we investigate the correlation of electrical properties and structure of 1-4 nm thick SiO2 grown on H-passivated Si(100) for ultra-thin gate applications. Ordered (1×1) Si(100) stable in ambient air is obtained at room temperature by wet chemical cleaning. Ion Beam Analysis using a combination of ion channeling and 16O(α,α)16O nuclear resonance yields Si areal densities lower than that of a bulk-terminated Si crystal as calculated by Monte-Carlo simulations. This result indicates shadowing of Si substrate atoms by Si atoms in the thermally grown oxide. Detection of order by ion channeling is supported by Reflection High Energy Electron Diffraction (RHEED). C-V and I-V measurements are generally inconclusive for ultra-thin (1-2 nm) oxides because of leakage and breakdown. Surface charge analysis enables a comparison between ordered oxides and conventional oxides. The results are promising.

Layer-by-layer oxidation of Si(111) and (001) surfaces has been studied by using scanning reflection electron microscopy (SREM). We found that SREM images reveal interfacial structures of the SiO2/Si system. Our results showed that the initial step structure of Si substrates was preserved at SiO2/Si interfaces and that interfacial steps did not move laterally during oxidation. We also observed a periodic reversal of terrace contrast in SREM images during the initial oxidation of Si(001) surfaces. These results indicate layer-by-layer oxidation of Si surfaces, which is promoted by the nucleation of nanometer-scale oxide islands at SiO2/Si interfaces. In addition, we investigated the kinetics of initial layer-by-layer oxidation of Si(001) surfaces. We found that a barrierless oxidation of the first subsurface layer, as well as oxygen chemisorption onto the top layer, occur at room temperature. The energy barrier of the second-layer oxidation was found to be 0.3 eV. The initial oxidation kinetics are discussed based on first-principles calculations. Moreover, we confirmed that the layer-by-layer oxidation of Si surfaces holds true for conventional furnace oxidation.

This paper discusses chemical bonding effects at Si-dielectric interfaces that are important in the implementation of alternative gate dielectrics including: i) the character of interfacial bonds, either isovalent with bond and nuclear charge balanced as in Si-SiO2, or heterovalent, with an inherent mismatch between bond and nuclear charge, ii) mechanical bonding constraints related to the average number of bonds/atom, Nay, and iii) band offset energies that are reduced in transition metal oxides due to the d-state origins of the conduction band states. Applications are made to specific classes of dielectric materials including i) nitrides and oxide/nitride stacks and ii) alternative high-K gate materials.

We consider nitrogen profiling in oxynitrides to be the key technology for next generation Flash Memories, because of its ability to suppress the generation of traps in tunnel oxides. We are trying to develop an oxynitriding technique for tunnel oxides that uses nitric monooxide. This time, we tried to control nitrogen profile in oxynitrides by using reoxidized oxynitride process. By using a three- step oxidationoxynitridation-reoxidation process, we attempted to systematically tune oxidation conditions, to obtain a satisfactory tunnel oxide/Si interface and SILC characteristics. Highly reliable tunnel oxide for flash memory has been achieved using recently developed reoxidized oxynitrides processing, which is characterized by wet oxidationoxynitridation-dry oxidation. This process yields excellent characteristics, such as low oxide trap formation, low leakage current, and high charge to breakdown (Qbd). This three-step oxynitride process is best suited for flash memories having superior Program/Erase (P/E) cycling endurance and data retention characteristics. In addition, I will propose the optimum conditions for the reoxidation process.

In this paper, we propose an original approach of the silicon (100) dry thermal oxidation modeling that is capable to reproduce the oxidation dynamics at the atomic level and at a large scale comparing with ab initio methods. This approach is based on the use of a Monte Carlo procedure to manage the temporal aspect. In conjunction with experimental literature data, first principle calculations have been carried out with the objective of isolating some elementary oxidation mechanisms, i.e. basic atomic movements and their corresponding energies. This preliminary list of mechanisms is discussed in detail. A growth mechanism allowing the oxide defect generation is proposed. Finally, we present Monte Carlo calculations with the implemented mechanisms where at least three silicon layers are oxidized.

A decrease in the amplitude of Fowler-Nordheim current oscillations (FN-CO) due to interface roughness is observed for thin film (∼40Å) metal-oxide-semiconductor (MOS) devices, only when the interface has high spatial complexity. Previous studies have shown no measurable changes in FN-CO's resulting from the oxidation of purposely roughened Si surfaces. The present research continues with an FN-CO study using Si surfaces with roughness of higher spatial complexity than the previous studies. The spatial complexity of the purposely roughened Si surfaces was compared using the fractal dimension (DF). Atomic force microscopy (AFM) was used to measure the interface topography, and fractal dimension (DF) was used to describe the surface complexity while root-mean-square (RMS) roughness was used for obtaining vertical information of the roughness. It was found that the oscillation amplitude decrease substantially with an increase of DF but with no dependence on RMS.

This paper discusses the simulation needs of deep-submicron MOSFETs beyond the 100 nm technology generation where the tunneling of carriers through the gate dielectric will become a vital issue in device design, optimization, and characterization. We present simulation results of Tunnel-PISCES, a MOSFET device simulator where tunneling in the gate dielectric is implemented in a self-consistent manner with the device equations in the substrate. Simulation results of trends in the gate, substrate, and drain currents with oxide scaling are presented. The drain-current turnaround effect is explained by considering the role of the voltage drop across the polysilicon gate resistance in determining the device gate tunneling conditions.

Mesarjian et al. were the first to recognize the effects of suboxide interfacial transition regions at Si-SiO2 interfaces on tunneling oscillations in the Fowler-Nordheim regime. This paper extends these ideas to the direct tunneling regime and focuses on differences in interfacial transition regions between Si-SO2 interfaces with, and without monolayer level interface nitridation. Tunneling currents in both the direct and Fowler-Nordheim tunneling regimes are reduced by monolayer level interface nitridation for PMOS and NMOS devices with the same oxide-equivalent thickness. This paper develops a modified barrier layer model based on analysis of XPS results that accounts for these reductions in current in the direct tunneling regime.

We report the electrical characterization of a direct tunneling diode structure that incorporates a multilayer dielectric. The dielectric consists of a stack of two thermally grown, ultrathin SiO2 layers, each ∼3.5 rin thick, separated by a deposited, continuous, undoped, ultrathin nanocrystalline Si layer ∼5.0 nm thick. Electrical measurements of this structure are reported for both n-type and p-type Si substrates. We find that the room temperature transport through this structure is accounted for by describing the intermediate Si layer as a quantum well with a continuum of states, and by otherwise assuming bulk properties for the ultrathin layers, such as the existence of a bandgap in the Si well and the usual Si-SiO2 interface potential barrier height at all interfaces. This structure is expected to be useful as the active dielectric in nonvolatile memory devices.

The conduction band and valence band electron tunneling currents in ultra-thin SiO2 films at the transition from direct to Fowler-Nordheim tunneling regimes are studied. The slopes of the current voltage characteristics agree well with the simulations performed. The Stress-Induced Leakage Current (SILC) behavior is quite similar for both conduction and valence band currents even if the amplitude of the valence band SILC is much lower. We show that a linear dependence exists between the stress-induced interface trap density and both valence and conduction band SILC. A new model of SILC is also proposed.

Using a leakage-compensated charge (LCCV) technique to obtain static capacitance-voltage (C-V) curves, we extend the standard high-low C-V method for determining the interface state level density, Dit as a function of energy in the silicon band gap to metal-oxide-silicon capacitors in the direct tunneling regime (oxide thickness ∼<3.5 nm). The LCCV technique yields true static C-V curves for oxides at least as thin as 2.8 nm, where the tunnel leakage current is so high that the usual quasistatic C-V measurement is not possible. As applications of this method, Dit is compared for fresh oxides of different tunnel thickness, and Dit is measured before and after constant voltage stress of a 3.5-nm oxide. The stress results indicate, as in other work on thicker oxides, that interface traps are created during the stress, with peak densities both below and above midgap. This approach is expected to be useful for evaluating both ultra-thin oxides and leaky alternate gate dielectrics.

Thin oxides (3-20 nm) have been grown on nitrogen-implanted silicon by regular thermal oxidation and by rapid thermal oxidation in dry oxygen. The implant dose ranged from 1×1013 to 1×1015 cm−2. Significant oxidation retardation has been observed for nitrogen doses above 1×1014 cm−2. Al-gate MOS capacitors were fabricated to characterize the thin oxides for dielectric breakdown strength and leakage. Gate oxides, grown by our standard baseline process, exhibited a decrease in their dielectric strength from ∼10 MV/cm for thickness > 18 nm to 3-4 MV/cm for < 8 nm thickness. The nitrided oxides maintained their integrity at ∼10 MV/cm as thickness decreased, unless a critical dose was exceeded, which resulted in poor performance. These electrical measurements indicate that a nitrogen implant, prior to gate oxide growth, is beneficial to oxide integrity.

The structure of the SiO2/Si interface has been probed using X-ray photoelectron spectroscopy (XPS) and analyzing Si 2p core level spectra. The XPS analyses on as grown samples of nitrided and un-nitrided oxides of similar thickness (3 nm) do not show any significant suboxide peaks corresponding to Si1+, Si2+ or Si3+ states at the interface. However, on exposing the surface to argon ion sputtering at 3.5 kV for 30 seconds, prior to XPS analysis, the presence of suboxides at the SiO2/Si interface is detected. The SiO suboxide (Si2+) density in oxides grown on nitrogen-implanted silicon is much less than that in the oxides grown on unimplanted silicon. This is a direct evidence of sputter damage resistance of nitrided thin oxides. The beam-induced damage in the oxide is also found to be less in nitrided oxides. The suppression of suboxide formation at the interface due to the presence of nitrogen appears to be responsible for the enhanced reliability of nitrided oxides.

The reaction of molecular hydrogen with Pb defects at the (111) Si/SiO2 interface has been studied using a remote radio frequency (RF) probe to continuously monitor the rate of removal of electrically active defects. The kinetic parameters calculated from these experiments are compared with the earlier work of Brower and Stesmans. Although the data confirms the non-exponential nature of the reaction reported by Stesmans the activation energy of the process is found to be somewhat different.

We have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

In this paper, a significant degradation under hot hole injection is observed in P+ -poly PMOSFETs with oxynitride gate dielectrics. In our study, both oxynitrides formed by gate oxide grown on Nitrogen Implanted Si Substrates (NISS) and NO-annealed SiO2 oxynitride gate dielectrics are used and compared to control SiO2 gate dielectrics of identical thicknesses. A physical model responsible for such enhanced degradation in PMOSFETs with oxynitride gate dielectric is proposed. It is shown that the hole injection barrier lowering as a result of the nitrogen-rich layer at the SiO2/Si interface in oxynitride is responsible for such enhanced degradation.

The greatest benefits of nitrogen incorporation into gate dielectrics may be obtained by placing nitrogen preferentially at the interfacial regions of the dielectric film. One method of distributing nitrogen in this manner is by using a three-step thermal process consisting of 1.) oxynitridation in NO, 2.) subsequent reoxidation in O2, and 3.) a final NO anneal. This study investigates the effect of NO processing on substrate/dielectric interface roughness and correlates that roughness with dielectric reliability. The initial NO-containing step can roughen the interface, as can subsequent reoxidation. Increased NO exposure yields a greater nitrogen content and a concomitant increase in interface roughness. These films show a degradation in charge to breakdown (Qbd) of at least an order of magnitude when compared with similarly prepared O2-oxide films. An O2/NO process produces films with interface roughness and Qbd comparable to that of pure SiO2, independent of nitrogen content. The oxynitride reliability depends on the exact scheme for incorporating nitrogen into SiO2.