One of the major challenges during recent years was to achieve the compatibility of III-V semiconductor epitaxy on silicon substrates to combine opto-electronics with high speed circuit technology. However, the growth of high quality epitaxial GaAs on Si is not straightforward due to the intrinsic differences in lattice parameters and thermal expansion coefficients of the two materials. Moreover, antiphase boundaries (APBs) appear that are disadvantageous for the fabrication of light emitting devices. Recently the successful fabrication of high quality germanium layers on exact (001) Si by chemical vapor deposition (CVD) was reported. Due to the germanium seed layer the lattice parameter is matched to the one of GaAs providing for excellent conditions for the subsequent GaAs growth. We have studied the material morphology of GaAs grown on Ge/Si PS using atomic layer epitaxy (ALE) at the interface between Ge and GaAs. We present results on the reduction of APBs and dislocation density on (001) Ge/Si PS when ALE is applied. The ALE allows the reduction of the residual dislocation density in the GaAs layers to 105 cm−2 (one order of magnitude as compared to the dislocation density of the Ge/Si PS). The optical properties are improved (ie. increased photoluminescence intensity). Using ALE, light emitting diodes based on strained InGaAs/GaAs quantum well as well as of In(Ga)As quantum dots on an exactly oriented (001) Ge/Si pseudo-substrate were fabricated and characterized.

The rapid expansion of SiGe technologies during the last decade essentially due to civil telecommunication's applications have led Si/SiGe based heterojunction bipolar transistors (HBTs) to excellent performance levels, allowing high frequency low noise circuit designs such as linear low noise amplifiers( RF noise) or also low-phase noise oscillators (LF noise). Among these technologies, the SiGe BiCMOS one integrates digital and RF functions on the same chip. Fast improvements of the technological process have been performed thanks to large efforts allowed to characterization and modeling of the devices. We have investigated on the influence of technological parameters such as Germanium profile, doping level and thickness of the base layer (5 different wafers) on the dynamic and high frequency noise performances to converge towards the optimum technological process (now available with the BiCMOS6G processed by ST microelectronics). We made use of scattering parameters [S] measurements on the devices to extract the electrical parameters of our small signal model. The high frequency noise parameters based on the electrical model (with noise sources added to the junction, resistances) are simulated and compared with the measured noise parameters of the devices. The four noise parameters (Fmin, Rn, and complex Γopt) measurements have been performed from 1 GHz to 12 GHz, and the dynamic S parameters measurements have been realized in the 40 MHz-40 GHz range. These models have been used to enable the identification of the limiting parameters on the dynamic performances and on the high frequency noise parameters.

We have studied the strain state, film and surface morphology of SiGe virtual substrates (Ge concentrations in-between 20% and 55%) grown by reduced pressure – chemical vapor deposition. The macroscopic degree of strain relaxation of those virtual substrates is equal to 97.2 ± 1.5%. The misfit dislocations generated to relax the lattice mismatch between Si and SiGe are mostly confined inside the graded layer. Indeed, the threading dislocations density obtained for Ge concentrations of 20% and 26% is indeed typically of the order of 7.5 ± 2.5 105 cm−2. Low surface root mean square roughness have been obtained, with values in-between 2 and 5 nm. In order to check the electronic quality of our layers, we have grown a MODFET-like heterostructure, with a buried tensile-strained Si channel 8 nm thick embedded inside SiGe 26%. We have obtained a well-behaved 2-dimensional electron gas in the Si channel, with electron sheet densities and mobilities at 1.45K of 5.4×1011 cm−2 and 212 000 cm2 V−1 s−1, respectively.

In advanced CMOS technology nodes one may achieve further enhancement of device performance by carrier mobility modification in the transistor channel. The carrier mobility enhancement can be realized by formation of strained silicon layers on a Si1−xGex strain relaxed buffer. Formation of source and drain extensions on such structures need to satisfy one additional requirement, the formation process, including the activation related thermal budget should not relax the strain in the channel. In this paper we separately investigate the role of amorphization during implantation, different doping impurities and thermal budget on the junction and the transistor channel regions properties. Two approaches of dopant activation are discussed: low temperature solid phase epitaxial regrowth and high temperature conventional spike.

Precise determination of the Ge outdiffusion into the Si cap in strained Si/SiGe structures and the depth distribution of dopants have been critical to the industry and a challenge to the SIMS community. Will the rough cross-hatch surface topography degrade the SIMS depth resolution, or alter the accuracy of the depth profile?

Here we report on a novel AFM approach to show that the SIMS measurement process results in conformal sputtering. Therefore, maintaining excellent depth resolution and the depth distribution accuracy capabilities of SIMS for these material systems.

Atomic-order surface reaction processes on the group IV semiconductor surface are formulated based on the Langmuir-type surface adsorption and reaction scheme. In in-situ doped Si1−xGex epitaxial growth on the (100) surface in a SiH4-GeH4-dopant (PH3, or B2H6 or SiH3CH3)-H2 gas mixture, the deposition rate, the Ge fraction and the dopant concentration are explained quantitatively assuming that the reactant gas adsorption/reaction depends on the surface site materials and that the dopant incorporation in the grown film is determined by Henry's law. Self-limiting formation of 1-3 monolayers of group IV or related atoms in the thermal adsorption and reaction of hydride gases (SiH4, GeH4, NH3, PH3, CH4 and SiH3CH3) on Si(100) and Ge(100) are generalized based on the Langmuir-type model. Epitaxial Si or SiGe grown on N, P or B layers already-formed on Si(100) or SiGe(100) surface is achieved. It is found that higher level of electrical active P atoms exist in such film, compared with doping under thermal equilibrium conditions. Furthermore, the capability of atomically controlled processing for doping of advanced devices with critical requirements for dopant dose and location control is demonstrated for the base doping of SiGe:C heterojunction bipolar transistors (HBTs). These results open the way to atomically controlled technology for ultra-large-scale integrations.

We describe novel 2-D structures that facilitate strain relief and allow us to obtain Ge epilayers that are free of defects. These structures can potentially absorb thermal expansion and lattice expansion mismatch as well as enable liftoff of heteroepitaxial layers for subsequent wafer reuse. Conventional lithography techniques were combined with reactive ion and wet-chemical etching to fabricate 2-D patterns of silicon posts. The dimensions of the posts were varied keeping the pitch (center to center distance) constant. Heteroepitaxial growth of Ge/SixGe1−x on these micrometer-scale structures was investigated. While, keeping the growth parameters constant, the geometry of the structures was varied to determine the optimum configuration for the highest quality heteroepitaxial growth. The quality of the Si1−xGex buffer system was investigated using high-resolution x-ray diffraction. Transmission electron microscopy (TEM) was used to analyze the epilayer cross-sections. Surface morphology was analyzed using scanning electron microscopy (SEM), atomic force microscopy (AFM) and optical microscopy. Our results show that the quality of the heteroepitaxial layers improves as the width of the posts in the 2-D pattern was decreased.

NMOS devices have been successfully fabricated on SSOI wafers. The SSOI wafer fabrication is by direct wafer bonding and wafer transfer by splitting of the strained Si on thin SiGe virtual substrate to an oxidized wafer. The thin SiGe virtual substrate is fabricated by strained SiGe deposition, H2+ implantation, and SiGe lattice relaxation anneal. This relaxation process creates a confined defect zone at the SiGe to Si substrate interface that ensures low defect strained Si growth. 10 μm by 10 μm NMOS SSOI devices show an improvement of 100% in drive current and 115% in transconductance. A near ideal subthreshold swing was observed on NMOS devices with channel length as short as 0.1 μm.

Strained Silicon On Insulator wafers are today envisioned as a natural and powerfulenhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, thisnew technology potentially combines enhanced devices scalability allowed by thin films andenhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate byexperimental results how a layer transfer technique such as the Smart Cut™ technology can be usedto obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments andcharacterizations will be used to characterize these engineered substrates and show that they arecompatible with the applications.

A contender for future generations of CMOS technology is the strained silicon (S-Si) MOSFET. The mobility enhancement in S-Si can be exploited to maintain the performance enhancements demanded by Moore's law with reduced critical dimensions. S-Si is obtained by growth of a thin Si layer over a thick virtual substrate (VS) of relaxed silicon-germanium (SiGe). The mobility of a surface channel MOSFET is dependent on the quality of the silicon-oxide (Si/SiO2) interface. Ge may out diffuse from the virtual substrate to the oxide interface causing an increase in trapping density. As the Ge content in the virtual substrate increases surface roughness also increases. These phenomena both lead to a reduction in mobility.

The study of a matrix of devices having variable Ge composition and S-Si thickness is crucial in deconvolving the contributions of Ge diffusion and wafer cross-hatching roughness on electrical parameters. Increasing VS Ge composition increases the Ge concentration at the SSi/SiO2 interface and cross-hatching amplitude whereas reducing S-Si channel thickness only increases Ge concentration at the S-Si/SiO2 interface and does not increase cross-hatch amplitude. Interface state density, drive current, gate leakage current, transconductance and carrier mobility data are presented for this two-dimensional space of VS composition and S-Si thickness. The relative importance of Ge diffusion and cross-hatching roughness can be seen in this data. The results of this study indicate a lower limit of 7 nm for the S-Si thickness and an upper limit of approximately 20 % Ge in the virtual substrate for the current processing technology. Understanding the performance-limiting mechanisms in S-Si is crucial in the optimisation of VS Ge composition and S-Si thickness for current and future generations of S-Si CMOS.

The use of laser Raman spectroscopy to assess the residual strain in strained silicon/silicon germanium devices is well established. The peak shift associated with the 520cm−1 silicon peak can be used to directly measure the strain in the cap layer provided that the strained silicon peak can be deconvoluted from the more intense Si in SiGe peak which occurs at slightly lower wavenumbers. However, though peak position gives a measure of the macrostrains in the layer it is not useful for the assessment of microstrains associated with point defects which may also influence device performance; such microstrains influence the intensity of the Raman peaks and can, in principle, be monitored by this method. In this study we have undertaken a study of peak shape as a function of processing conditions for strained silicon on SiGe. Changes in peak position may be correlated with macrostrains and macrostrain relaxation around extended defects such as dislocations. Changes in peak width can be correlated with processes which lead to changes in composition (e.g. germanium build-up in the surface after etching) and microstrain. Such changes are not necessarily correlated with changes in macrostrain but indicate that microstrain could also be an important factor influencing device performance.

Self-aligned ultra-high-speed SiGe HBTs were developed by using selective epitaxial growth (SEG) technology. The use of HCl-free SEG, incorporation of C, and optimization of doping profiles significantly improves the performance of the HBT, producing a transistor with a high cutoff frequency of 170 GHz and a maximum oscillation frequency of 204 GHz, for a minimum ECL gate delay time of 4.8 ps. This is applied in a 16:1 MUX with a maximum clock rate of 57 GHz. A 0.13-μm SiGe BiCMOS technology is also realized without any degradation of CMOS due to the high stability of SiGe HBTs. Furthermore, the structure of SiGe HBT is optimized for an emitter scaled down towards 100 nm, mainly through the use of a funnel-shaped emitter electrode to reduce both emitter and base resistances. High-speed operation of a static frequency divider demonstrates the advantage of SiGe HBTs for ultra-high-speed communications systems.

We perform a theoretical evaluation of the strain field in a p-channel transistor with silicongermanium (Si1−yGey) stressors in the source and drain regions. The strain field comprises a lateral compressive strain component and a vertical tensile strain component. The lateral strain component is larger in magnitude and more uniformly distributed as compared to the vertical strain component. The impact of transistor design parameters, such as the Ge mole fraction y in the stressors, the spacing L between stressors, the stressor depth, and the raised stressor height, on the strain field are investigated. Hole mobility enhancement larger than 30% is achievable wth L = 50 nm and y = 0.15. More aggressive mobility enhancement targets may be achievable by reducing the stressor spacing and employing a stressor with a larger lattice mismatch with the Si channel.

An overview of SiGe modulation-doped field-effect transistor (MODFET) technology is provided. The layer structures and mobility enhancements for both p- and n-channel modulation-doped quantum wells are described and compared to mobilities in Si/SiO2 inversion layers. Next, previous results on high-performance n- and p-MODFETs fabricated at IBM and elsewhere are reviewed, followed by recent results on laterally-scaled Si/SiGe n-MODFETs with gate lengths as small as 70 nm. We conclude with a discussion of the materials issues for the future vertical and lateral scaling of SiGe MODFETs.

Silicon-Germanium (SiGe) has become increasingly attractive to semiconductor manufacturers over the last decade for use in high performance devices. In order to produce thin layers of device grade SiGe with low concentrations of point defects and well-controlled doping profiles, advanced growth and deposition techniques such as molecular beam epitaxy (MBE) are used. One of the key issues in modeling dopant diffusion during subsequent processing is the concentration of grown-in point defects. The incorporation of vacancy clusters and vacancy point defects in 200nm SiGe/Si layers grown by molecular beam epitaxy over different buffer layers has been observed using beam-based positron annihilation spectroscopy. Variables included the type of buffer layer, the growth temperature and growth rate for the buffer, and the growth temperature and growth rate for the top layer. Different growth conditions resulted in different relaxation amounts in the top layer, but in all samples the dislocation density was below 106 cm−2. Preliminary results indicate a correlation between the size, type and concentration of vacancy defects and the buffer layer growth temperature. At high buffer layer growth temperature of 500°C the vacancy point defect concentration is below the PAS detectable limit of approximately 1015 cm−3. As the buffer layer growth is decreased to a minimum value of 300°C, large vacancy clusters are observed in the buffered layer and vacancy point defects are observed in the SiGe film. These results are relevant to the role played by point defects grown-in at temperatures below ∼350°C in modeling dopant diffusion during processing.

The strain relaxation and threading dislocation density of He-implanted and annealed SiGe/Si heterostructures have been studied. For He doses above a threshold of 8×1015 cm−2, the degree of strain relaxation depends primarily on the SiGe layer thickness; a similar degree of strain relaxation is obtained when the He dose and energy are varied over a relatively wide range. In contrast, the threading dislocation density is strongly influenced by the implantation depth. There is a strong correlation between the parameter He(SiGe), the He dose in the SiGe layer calculated from He profiles simulated using the program Stopping and Range of Ions in Matter (SRIM), and the threading dislocation density. We find that to achieve a low threading dislocation density, <5×107 cm−2, He(SiGe) must be less than 1015 cm−2. The strain relaxation mechanism is also discussed.

HfO2 films were deposited by reactive sputtering on Ge and Si substrates simultaneously, and we found not only the interface layer but the HfO2 film was thinner on Ge substrate compared with that on Si substrate. A metallic Hf layer has a crucial role for the thickness differences of both interface layer and HfO2 film, since those thickness differences were observed only when an ultrathin metallic Hf layer was predeposited before HfO2 film deposition. The role of metallic Hf is understandable by assuming a formation of volatile Hf-Ge-O ternary compounds at the early stage of film growth. These results show an advantage of HfO2/Ge over HfO2/Si systems from the viewpoint of further scaling of electrical equivalent thickness of the gate oxide films.

First results on formation of thin film GeOI structures by the Smart Cut™ technology are presented in this paper. Thin single crystal layers of Ge have been successfully transferred, via oxide bonding layer, onto standard Si substrates with diameters ranging from 100 to 200 mm. Compared to SOI manufacturing, the development of GeOI requires adaptation to the available germanium material, since the starting material can be either bulk Ge or an epitaxial layer. Some results will be presented for GeOI formation according to the different technological options. Germanium splitting kinetics will be discussed and compared to already published results. To show good quality of the GeOI structures, detailed characterization has been done by TEM cross sections for defect densities, interfaces abruptness and layers homogeneities evaluation. AFM was used for surface roughness measurements. These results help define procedures that are required to achieve large diameter high quality GeOI structures.

Strained SiGe was bonded to silicon dioxide by direct wafer bonding and Smart-cut technique. Strained SiGe with a graded 20%-30% Ge concentration was deposited by RTCVD on (100) Si to a thickness between 300nm to 350nm. H2+ for wafer splitting was implanted at an energy varied from 40 keV to 150 keV and a dose between 2.5E16 and 4.5E16 ions/cm2. SiGe relaxation was found to depend on wafer split temperature, and on post-split annealing temperature. SiGe relaxation of greater than 80% was observed after wafer splitting and annealing. Was it from gliding of a SiGe film weakly bonded to an oxide surface? In order to determine the relaxation mechanism, samples with different film structure were prepared. The films were then annealed at various temperatures. Some film showed a high degree of relaxation, and some showed minimal relaxation, depending mostly on hydrogen implant depth. The results indicated that the generation of dislocation is the possible cause of SiGe relaxation.

Strain relaxed Si1−xGex layers are attractive virtual substrates for the epitaxial growth of strained Si. Tensile strained Si has attracted a lot of attention due its superior electronic properties. In this study, the strain relaxation of pseudomorphic Si1−xGex layers grown by chemical vapor deposition (CVD) on Si(100) substrates was investigated after He+ ion implantation and thermal annealing. The implantation induced defects underneath the SiGe/Si interface promote strain relaxation during annealing via preferred nucleation of dislocation loops which form misfit dislocations at the interface to the substrate. The amount of strain relaxation as well as the final threading dislocation density depend on the implantation dose and energy. Si1−xGex layers with thicknesses between 75 and 420 nm and Ge concentrations between 19 and 29 at% were investigated. The strain relaxation strongly depends on the layer thickness. Typically the structures show ≈70 % strain relaxation and threading dislocation densities in the low 106 cm−2 range. AFM investigations proved excellent surface morphology with an rms roughness of 0.6 nm. The samples were investigated by Rutherford backscattering spectrometry, ion channeling, transmission electron microscopy and atomic force microscopy.