We present an optoacoustic method to non-destructively measure the average dimensions of a periodic array of simple structures with aspect ratios greater than 10:1, which are inaccessible to AFM techniques. The technique that we describe could be used as the basis of an inline metrology tool for wafer inspection. The samples examined were test structures with high precision lithographically defined lines of silicon dioxide deposited on a silicon substrate. The thickness of the silicon dioxide was around 400 nm, and the gaps between the lines ranged from 100 nm down to smaller than 40 nm. A drop of water was placed on the sample, and an optoacoustic transducer was placed on top; measurements were taken with a water thickness less than 1 micron between the optoacoustic transducer and the sample. The water filled the spaces between the lines due to the hydrophilic nature of the sample surface. Using the picosecond ultrasonics technique, acoustic pulses are generated in a special optoacoustic transducer, transmitted through a coupling fluid (water), scattered off of the sample being examined and then return to the transducer. The returning acoustic signal shows nanometer sensitivity to the height of the lines and the specific details of their profile.

We evaluated the effects of the edge degradation of diamonds in terms of their cutting ability from the viewpoint of mechanical, chemical and chemical-mechanical wear in chemical-mechanical polishing (CMP) systems for high-volume manufacturing. The results showed that both micro-chipping on the cutting edges of diamonds caused by a mechanical shock test and the rounding off of the sharp edges of diamonds in a marathon wear test degraded the pad cut rate, while no adverse effects on the cutting ability were observed during an acidic slurry immersion test. We also examined in situ coefficient of friction (COF) monitoring for use in identifying the tribology of the pad conditioning. Furthermore, we demonstrated the usefulness of measuring the height ratio of the asperity called “top surface area (TSA) ratio” as an appropriate topographical parameter to study the dependence of COF during conditioning on the decay of the tungsten removal rate. We presented a clear correlation between the pad cut rate degradation and the TSA ratio after CMP in order to elucidate an increase in the conditioning COF related to truncation of the asperity tip by wear and plastic deformation.

Wafer bonding using benzocyclobutene (BCB) has been discussed in the past for three-dimensional (3D) integration. This paper reports the development and characterization of a manufacturable BCB bonding process for 300 mm wafers using standard 300 mm tools. A systematic optimization approach has been developed to characterize the bulk properties of the BCB film that can be applied to various integration schemes. We specifically discuss one such application—handle wafer bonding. BCB bonding for a range of cross-linking levels has been investigated. The cross-linking level of BCB before bonding is determined using an infrared (IR) variable angle spectroscopic ellipsometer (VASE) technique. The impact of the BCB film preparation and bonding condition on bond quality is characterized using scanning acoustic microscopy (SAM) , IR microscopy, a razor blade test, and four-point bend methods. Based on the results, an optimum cross-linking level for BCB film before bonding was determined for 300 mm wafers to obtain void-free and dendrite-free bonds. Wafers bonded using the optimized BCB process conditions have successfully sustained backgrinding, dry thinning, and standard BEOL metallization steps.

The future resolution requirements for the semiconductor industry demand advanced lithographic techniques, such as immersion and extreme ultraviolet (EUV) technologies, which will increase the cost of microelectronics manufacturing. Currently, low-k dielectric materials, which are used as insulating layers between the copper wiring, are indirectly patterned using a set of sacrificial layers and etch processes. The sacrificial layers include a photoresist polymer that must first be imaged prior to transferring the pattern to the underlying layers, including the dielectric layer. In order to reduce the number of processing steps required for semiconductor manufacturing, we have developed a novel photo-patternable low-k dielectric material that (1) eliminates the need for sacrificial layers and (2) reduces the number of wafer processing steps. Silsesquioxane copolymers that undergo acid-catalyzed crosslinking when exposed to 193nm wavelength were synthesized. In addition to the direct photo-patternability, the patterned structures are suitable as a dielectric material with a dielectric constant as low as 2.4, and an appreciable elastic modulus (E > 4.0 GPa). These photo-patternable low-k materials represent a ‘greener' approach to semiconductor manufacturing which has the ability to reduce cost, waste materials, and energy consumption.

In this study, the temperature map distribution in the Sn3.0Ag0.5Cu solder bump with Cu column under current stressing is directly examined using infrared microscopy. It is the radiance changes between the different materials of the surface that cause the unreasonable temperature map distribution. By coating a thin layer of black optical paint which is in order to eliminate the radiance changes, we got the corrected temperature map distribution. Under a current stress of 1.15 × 104 A/cm2 at 100℃C, the hot-spot temperature is 132.2℃ which surpasses the average Cu column temperature of 129.7℃C and the average solder bump temperature of 127.4 ℃. Thermomigration in solder may still occur under a large current stressing.

We succeeded in fabricating ultra-thin (<3 nm-thick) layer on top of the surface of porous low-k. The roughness of the surface of porous low-k remains homogeneous even after covering by the thin layer. Furthermore, we found that such ultra-thin layer suppresses the diffusion of metal into porous low-k film. Concerning adhesion property, the abrasion between the thin layer and copper was not detected after annealing at 350 deg C in forming gas. TVS measurement suggested that pH control of solution is the key to reduce damages of porous low-k and mobile ions. We believe that such ultra-thin layer, which we propose here, has a potential as a pore seal layer for porous low-k films.

The mechanism of haze reduction during silicon polishing using a new generation of additives has been explored. These additives are thought to decrease haze by adsorbing to the wafer surface and increasing the activation energy of the reaction between the silanolates on the silica particle surface with the surface silicon. This leads to greater selectivity between the peaks and valleys resulting in a net decrease in surface roughness.

Ta family has been used as barrier to prevent Cu diffusion into interlayer dielectric in IC applications. Recent experiments demonstrated a more severe flatband voltage shift (ΔVFB) occurred for Ta/porous low k dielectrics/Si capacitors compared to that of Cu/porous low k dielectrics/Si capacitors after a moderate bias temperature stress (BTS). The flatband voltage shift under BTS was interpreted as the penetration of Ta ions into porous low k dielectrics. However, this interpretation has been under debate. In this paper, by using Secondary Ion Mass Spectrometry (SIMS) backside sputter depth profile technique, we report a direct evidence of Ta ions inside porous methyl silsesquioxane (MSQ) in a Ta/MSQ/Si structure after BTS.

In this presentation we will discuss polishing performance and related mechanistic aspects of several low solids, low or high pH slurries based on Lewis acids abrasives (TiO2, ZrO2, CeO2), activated by cationic homopolymers, and copolymers with acrylic functionality. In a typical example, a formulation containing 0.5% ZrO2 interacting with 75 ppm cationic copolymer, at pH = 4, resulted in a SiO2 removal rate increase of 34% and a nitride removal rate increase of 97%, as compared with the control lacking the cationic copolymer. We will provide a complex variety of analytical evidence and particle and wafers surface measurements (FT-IR, GPC, surface energy) in order to support our mechanistic hypotheses. We will show with this unique system that 1:1 selectivities of oxide and nitride can be achieved with high removal rates.

Studies of the wafer edge uniformity step by step, from hard mask deposition, reactive ion etch, electroplating to post Cu CMP had been done using scanning electron microscopy (SEM) measurements, showed that the major wafer non-uniformity comes from the Cu CMP step. Improvement of Cu CMP edge uniformity had been achieved through engineering of platen 1 using real time profile control as well as CMP head zone pressure adjustment and platen 3 slurry optimizations

Large particles in fumed silica dispersions were characterized by sedimentation, light scattering techniques, Transmission Electron Microscopy (TEM), and lacunarity. Applying centrifugation to fumed silica dispersions generated differences in sedimentation rates of large particles. The sedimentation rates of the large particles were affected by morphological differences and the particles remaining in the supernatant displayed buoyant behavior. The large particle morphology varied from branch like aggregates containing large primary particles to particles comprised of highly coalesced, tightly packed small primary particles. The results indicate the presence of different types of large particles in fumed silica dispersions to which conventional large particle characterization is unable to distinguish.

The Joule heating effect at various stages under electromigration of flip-chip Sn3.5Ag solder joints was investigated under a current of 0.5 A at 100°C. During various stages of electromigration, voids may form and propagate and Joule heating effect may vary at different void sizes. To verify the void nucleation and propagation on Joule heating effect during electromigration process, the solder bump was stressed for different lengths of time and then examined by Kelvin bump probes and infrared microscopy. We found that voids started to form at approximately 1.2 times of the initial bump resistance. Then the voids propagated when the bump resistance increased. In addition, the temperature of the solder joints increased with the bump resistance and the increase of current stressing time. It increased very slowly in initial stages. In the last stage, the temperature of the solder bump increased rapidly due to the increase of the bump resistance and the local Joule heating effect.

Micro-texture dependence of both the mechanical and electrical properties of electroplated copper thin films was discussed experimentally considering the change of their micro texture caused by thermal history after the electroplating. Both the static and fatigue strength of the films changed drastically depending on the micro texture and it was found that there were two fatigue fracture modes in the films. One was a typical ductile intragranular fracture and the other was brittle intergranular one. The reason for the variation of the strength of the electroplated copper thin films was attributed to the variation of the average grain size and the characteristics of grain boundaries. In addition, the electrical reliability of the electroplated copper interconnections was discussed under electromigration tests. Though abrupt fracture mode due to the local fusion appeared in the as-electroplated films, the life of the interconnections was improved significantly after the annealing at temperatures high than 200°C. Typical change of the surface morphology of the film, i.e., the formation of voids and hillocks were observed on their surfaces after the annealing. This was also caused by the change of the micro texture from fine grains with porous grain boundaries to coarsened columnar grains with rigid grain boundaries. However, the stress-induced migration appeared in the annealed narrow interconnections, in particular. This was because of high tensile residual stress occurred in the film due to the constraint of the shrinkage of the films by rigid oxide around them. These results clearly indicated that the control of both the micro-texture and residual stress is indispensable for improving the reliability of the interconnectins.

Organosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.

Device scaling predicts that copper barrier layers of under 3 nm in thickness will soon be needed in back-end processing for integrated circuits, motivating the development of new barrier layer materials. In this work, nanoscale organic thin films for use as possible copper diffusion barrier layers are deposited by molecular layer deposition (MLD) utilizing a series of self-limiting reactions of organic molecules. MLD can be used to tailor film properties to optimize desirable barrier properties, including density, copper surface adhesion, thermal stability, and low copper diffusion. Three systems are examined as copper diffusion barriers, a polyurea film deposited by the reaction of 1,4-phenylene diisocyanate (PDIC) and ethylenediamine (ED), a polyurea film with a sulfide-modified backbone, and a polythiourea films using a modified coupling chemistry. Following deposition of the MLD films, copper is sputter deposited. The copper diffusion barrier properties of the film are tested through adhesion and annealing tests, including 4-point bend testing and TEM imaging to examine the level of copper penetration.The promise and challenges of MLD-formed organic copper diffusion barriers will be discussed.

In situ investigations of the chemical and mechanical mechanisms during CMP processes require analytical access to the wafer surface while interacting with the slurry and the pad under polishing conditions. In this study me make use of novel, specifically prepared, and self-designed Si wafer called microstructured single reflection elements (mSRE) utilizing the IR transparency of silicon [1]. The mSRE's enable in and ex situ attenuated total reflection (ATR) Fourier transform infrared (FTIR) investigations at the interface between silicon and the ambient with an enhanced usable spectral range. So, a thin silicon oxide layer or the polishing slurry can be investigated in the entire mid and far infrared spectral region. These mSRE wafers were placed at a simple reflection accessory of a FTIR spectrometer and either wet etched by a buffered oxide etch or polished using a CMP equivalent polishing configuration. During CMP the change of typical vibration bands of SiO2 layers and slurry constituents are observed. It was shown that the sensitivity as well as the surface selectivity of the experimental setup enables slurry and thin-film characterisations within the thickness range of monolayers. Surprisingly, the spectral features of the pad have not been observed during the polishing investigations.

The focus of this work is wafer retaining rings and their impact on chemical mechanical planarization (CMP) process stability, yield, and overall cost of ownership (CoO). The study looks at various CMP retaining ring materials and processing methods. Tribological investigations as well as wafer processing are critical to understand the retaining ring and polishing pad environment. Interactions at the ring/pad interface have a major effect on the planarization and defectivity of a polished wafer. Shear and normal forces at this interface, as well as temperature and lubrication regimes, were monitored to establish an empirical model. All process conditions equal, the material properties of retaining rings govern the coefficient of friction (COF) in the ring and pad contact area. Present study demonstrates a lower COF to be an indicator of extended ring lifetime, decreasing WTWNU and removal rate (RR) variation. The study correlates the findings on wafer level data from high volume manufacturing fabs with empirical data generated using applications lab tribological equipment to understand the on-wafer performance as a function of retaining ring material. The study's further aim is to understand for specific applications, the material interactions on-wafer using various retaining ring materials. CMP process optimization can be attained with a better understanding of retaining ring design and material characteristics, as well as polishing head and slurry parameters.

This study discusses topography specifications for 22 nm and beyond CMP process and presents recent experimental data. We evaluated local topography impact on CD development in the subsequent layer using specially designed 22-nm test patterns. A wide range of localized erosions were generated in CMP within a single exposure field to avoid any focus-correction effect by the scanner or any other scanner-induced focus change between different levels of local erosion. Local erosions were measured by atomic force microscopy (AFM) after each process step from CMP to lithography to identify the local planarization effect from other film coatings between CMP and lithography. Post-litho CD inspection was done in the subsequent layer over the local erosion areas. Using experimental results, the paper also discusses BEOL pattern design rule for maximizing the process window.

In this paper, the authors introduce and present some findings on an alternative non-contact material removal technique. Material removal is made possible by utilizing the electrokinetic and hydrodynamic effects of suspended particles to manipulate their trajectories to impact onto the surface of the workpiece. The research was previously demonstrated and reported where the removal rate can be precisely controlled by varying the electrical field and the flow rate of the slurry across the surface of the workpiece. New findings are reported on the application of the technique to different materials that will highlight the attractiveness of this alternative approach to producing surfaces with roughness in the order of nanometres.

We describe the concept of a 3D self-folding package (SFP) for sensors and electronic devices. The strategy is based on a self-assembly strategy wherein 2D panels interconnected with hinges spontaneously fold-up when they are released from the substrate; self-folding can be triggered by temperature or selected chemicals. The strategy enables packaging of devices in porous polyhedral geometries that can either be untethered or substrate-bound. Self-folding can enable packaging of devices in small 3D form factors and may enable efficient cooling due to porosity. The utilization of this self-folding platform to enable 3D packaging of cantilever sensors and magnetic field sensitive strain gauges is summarized.