Further improvements in CMOS circuit performance such as switching speed and power reduction will rely on the use of silicon on insulator (SOI) substrates with decreased functional layer thicknesses. According to the International Technology Roadmap for Semiconductors (ITRS), the silicon and buried SiO2 (BOX) layer thicknesses for a fully depleted device should be in the ranges of 10–16nm and 24 – 40nm by 2005, respectively. A key issue for fully-depleted CMOS transistors is control of such ultra-thin layer thicknesses and their uniformity along with other parameters such as surface and interface roughness. This poses a challenge to metrology, especially to conventional reflectometry technique because the layer thicknesses must be determined with angstrom precision for both silicon cap and SiO2 box layer.

Spectroscopic ellipsometry (SE) is an optical and non destructive technique for determining thin film thickness and material optical properties. Because ellipsometry measures the change in the polarization state for both the amplitude ratio of the p to s polarizations, and in the phase retardation, it provides a precise way to characterize such ultra thin SOI stacks. Comprehensive characterization results for a number of thin and ultra thin SOI stacks with different thickness ranges will be presented together with measurement repeatability results relevant to the film thickness process tolerances. In addition, characterization results for advanced device applications such as strained silicon-on- Si1−xGex-on-insulator (SSOI) will also be shown, demonstrating the use and capability of spectroscopic ellipsometry for precise determination of layer thickness, material composition, interfacial layers, etc. Principles and advantages of the technique will also be discussed in the presentation.

A study of metal-insulator-semiconductor (MIS) structures based on SiNx, SiO2/SiNx and SiOxNy films deposited on silicon by electron cyclotron resonance plasma-enhanced chemical vapour deposition (ECR-PECVD) is presented. Interface trap densities measured by deep level transient spectroscopy (DLTS) are higher for silicon oxynitride-based MIS capacitors than for silicon nitride and silicon oxide-silicon nitride-based ones. However, conductance transient analysis demonstrated that Al/SiNx/Si devices exhibit the highest disordered-induced gap states (DIGS) density, whereas the lowest one corresponds to Al/SiNx/SiO2/Si, and silicon oynitride-based MIS capacitors show an intermediate behaviour. In addition, thermal treatments applied to Al/SiOxNy/Si samples reduce DIGS densities to values even lower than those corresponding to Al/SiNx/SiO2/Si devices.

In order to obtain a controllability in the nitrogen depth profile in the oxy-nitride gate dielectrics which has been known to have a strong effect on MOS reliability, micro second ordered pulse was used for the inductive coupled plasma source in our pulse time modulated plasma. The radio frequency (RF) of source plasma and pulse frequency were 12.56 MHz and 10 kHz (100 micro second), respectively. Pulse duty ratio was varied from 20 to 100 %. 1.7nm thick thermal silicon dioxide films were subjected to the pulse time modulated plasma and analyzed by SIMS to see the depth profile of nitrogen. A new finding is that both the concentration and the peak position of nitrogen atoms in silicon dioxide films depend on the pulse duty ratio and plasma radiation time. NBTI lifetime was improved with decreased interface state density. We also used this technique to high-k material and investigated process characteristics of nitridation

Growth behavior and film properties of ultra-thin Si3N4 layers formed by RTN (rapid thermal nitridation) were characterized. The self-limiting growth characteristics of the RTN process are appealing for precise thickness control in the range of 0.5–2.5nm. From SCA (surface charge analysis), the existence of negative fixed charge and electron traps in nitrides was found, in contrast to positive fixed charge and hole traps in oxides, and improvements in interface properties were seen after high temperature annealing. From annealing ambient dependences, the physical origin of the electron traps is likely N-H bonds in the nitride films. AFM (atomic force microscopy) analysis revealed that an atomically flat nitride surface is obtained by post-nitridation spike annealing, but a longer anneal leads to a rougher surface. Effectiveness of ultra-thin nitride barriers against boron penetration from a p+ poly-Si gate was also confirmed by SRA (spreading resistance analysis).

The synthesis and properties of oxide-based thin film transistors (TFTs) is reported using pulsed laser deposition. The field effect transistors use ZnO as the channel material. Low leakage current density is achieved with amorphous (CeTb)MgAl11O19 (CTMA) serving as the gate oxide, whose dielectric strength is measured to be > 5MV/cm for structures fabricated on Indium Tin oxide (ITO) substrates. Capacitance-voltage properties show that n-type active layers are realized with undoped ZnO. Charge densities in undoped ZnO are measured to be 1018 to 1019 / cm3 using Hall measurement and CV plots. Current-voltage measurements for TFT operation are reported. Channel materials on patterned substrates show high conductance and modulation of channel conductance. C-V measurements with MOS structure using doped ZnO and ZnxMg1-xO will also be described. The properties of depletion mode TFTs fabricated with doped and undoped oxide channel will be discussed in detail.

HfO2 thin films were grown by atomic layer deposition on Si, Ge, GaAs and GaN substrates, using Hf(OtBu)2 (mmp)2 and HfCl4. The results show that this combination of precursors promotes a conformal and smooth growth of HfO2 films on all substrates. As grown films in the thickness range of 10–20 nm have the same electronic density and smooth surfaces. Films 20 nm thick are polycrystalline with the monoclinic structure, whereas the crystallized fraction in the 10 nm thick layers is much lower. The HfO2 /Ge interface is remarkably sharp. The dielectric constant of the HfO2 films is 15. Low density of interface states and oxide fixed charges are obtained for the films grown on Si. The optimization of the HfO2 interface with the other substrates requires more effort.

We report on the fabrication of p-ZnO films by thermal oxidation of Zn3N2 deposited by reactive rf sputtering. With additional chromium doping we achieved p-type conductivity with the hole concentration ∼5×1017cm−3 and the mobility of 23.6 cm2/Vs at room temperature. We developed a method of surface passivation of p-ZnO that maintains its p-type conductivity over time-scale of months.

With alternating exposure of Si (100) substrates to tri (t -butoxy) silanol and anhydrous zirconium nitrate, mixed films of zirconia and silica were deposited at 162°C. The films were atomically smooth and their thickness was uniform across the entire substrate. The maximum growth rate of 12 Å/cycle implies deposition of more than one monolayer per cycle. A singular reflection in the low angle X-ray scattering pattern indicates an ordered bi-layer structure. Similar nanolaminate structures were also formed using anhydrous nitrates of hafnium and tin.

We introduced high-k Al2O3/Si3N4 buffer layer in MFIS (Metal-Ferroelectric-Insulator-Semiconductor) devices to reduce the leakage current though the buffer (I) layer. We prepared the buffer layer by nitridizing Si substrate by atomic nitrogen radicals and then deposited Al2O3 film using ALD (Atomic Layer Deposition) technique. The interface state density between the ALD-Al2O3/Radical-Si3N4 stacked insulator and a Si substrate is as low as 1011 cm−2eV−1. The current density less than 10−9 A/cm2 is realized under the 1V bias application using films with the capacitance density of 12fF/mm2. The c-axis oriented Bi3.45La0.75Ti3O12 (BLT) ferroelectric films were deposited to make MFIS structure. With this structure, we obtained the retention time as long as 1.5×106 sec (about 17 days). This excellent retention character is attributable to the high insulating property of the ALD-Al2O3/Radical-Si3N4 stacked insulator and also attributable to the perfect elimination of defects at the interfaces in the MFIS structure.

We have fabricated and characterized Pt (60nm) / (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT, 130nm) / Pt (60nm) / Ti (10nm) / SiO2 (10nm) / p-Si (MFMIS:metal-ferroelectric-metal-insulator-semiconductor) structure FETs. The area ratio, the ratio of SSBT capacitor area to SiO2 capacitor, is varied from 1 to 15 in the MFMIS-FETs. It is demonstrated that MFMIS-FETs with area ratio of 6 have memory window of 0.5V with supply voltage of 5 V. Dependence of memory window on the area ratio is discussed.

At present, new high-k dielectric materials are being intensively investigated to replace the silicon dioxide as gate dielectric for the next generation of electronic devices. Several candidate materials (such as ZrO2, HfO2, Al2O3) and deposition processes are currently under investigation. Because the layer thickness which is required in the next generations of devices is of the order of few nanometers, a precise determination and control of layer thickness will be mandatory. Although spectroscopic ellipsometry (SE) is well established non-contact, non-destructive and precise technique for determining thickness and optical properties of thin films, it becomes more difficult to obtain this information unambiguously and simultaneously for ultra-thin films with traditional SE alone because of possible high correlations between film structure and optical properties. The grazing x-ray reflectometry (XRR) is a complementary nondestructive optical technique and can be used to unambiguously determine ultra thin film thickness accurately. Combined with ellipsometry technique together, it will provide a promising way to characterize high-k gate dielectrics including thickness, roughness, interfacial layers and material composition information etc. In this paper, the principles for both SE and XRR will be briefly reviewed and limitation of each technique will be discussed. Following the high-k gate dielectric exploration and development, examples of using the combined SE/XRR techniques will be presented.

HfO2 dielectric layers have been grown on p -type Si(100) by plasma enhanced chemical vapor deposition (PE-CVD), using Ar-O2 plasmas and hafnium(IV) tetra-t -butoxide as precursors. In-situ control of the plasma phase is carried out by optical emission spectroscopy (OES) and quadrupolar mass spectrometry (QMS).

Structural and optical properties of the HfO2 layers and of the HfO2/Si interface are investigated by spectroscopic ellipsometry (SE) in the photon energy range 1.5–6.0 eV‥ SE data are corroborated by results obtained from glancing incidence X-ray diffraction (GIXRD), atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS).

The effect of the substrate temperature (RT-250°C) and precursor flow on the thickness of interfacial SiO2 layer and on the HfO2 microstructure is investigated. The growth dynamics of HfO2 film and SiO2 interface layer is also discussed.

The present paper establishes some required elements from both Quantum calculations and Kinetic Monte Carlo Modeling to perform full atomic scale simulations of Zirconia and Hafnia Atomic Layer Deposition (ALD) on Silicon technology process. In this view, we present quantum cluster calculations that investigate reaction pathways being part of the chemical reactions taking place at the different stages of the ALD growth. In particular, we detail ongoing research effort on the hydrolysis of adsorbed HfCl3 and ZrCl3 on ultra-thin SiO2. At very low water dose, the hydrolysis appears to be un-favourable. The complete reaction pathways with their associated activation barrier are detailed. We then show that actual available mechanisms emanating from quantum calculations are not sufficient to give a coherent picture of the layer structuring through a Kinetic Monte Carlo technique with the hope of giving new directions for further quantum studies.

We have investigated the influence of nitrogen incorporation into the HfAlOx film prepared by LL-D&A process with NH3 annealing step on structural change and electrical properties. Also, we have evaluated the effects of PDA treatment on electrical properties. Nitrogen concentration in HfAlOx(N) film was enhanced with increasing the NH3 annealing temperature. The shift of Hf 4f average binding energy towards lower side was observed in proportion to nitrogen concentration in HfAlOx(N) film. This result indicates the partial change of the local coordination from O-Hf-O to O-Hf-N. The increase of O-Hf-N component drastically degraded the gate leakage current in HfAlOx(N) film. Nitrogen atoms still maintained in HfAlOx(N) film even after PDA at 850°C in O2 ambient. PDA treatment at higher temperature after D&A(NH3) process improved the flat-band voltage shift and the electron mobility.

An investigation of metal-insulator-silicon capacitors, utilizing single crystal (La0.27Y0.73)2O3 as the insulator is presented. Crystalline insulators are of interest because of the possibilities of obtaining an atomically flat interface and entirely eliminating the presence of dangling bonds at the interface.

Capacitance – voltage measurements performed on MIS capacitors demonstrate a dielectric constant of 11.4 and suggest the absence of any interfacial silicon oxide layer. The equivalent oxide thickness of the sample with the thinnest dielectric layer is 15 Å. The density of interface states for the best samples is found to be in the mid 1012 cm−2eV−1 range and did not vary significantly after typical annealing treatments.

High quality HfSiON/SiO2 gate dielectrics were successfully formed using a hot wall batch system, which is suitable for mass production. The carbon contamination at HfSiON/SiO2 interface was reduced by a sequential process of the interfacial layer (IL) formation and HfSiOx metal organic chemical vapor deposition (MOCVD). The O3 treatment was found effective to reduce the residual carbon and hydrogen, while the NH3 treatment made the HfSiOx to be HfSiON, which was effective to prevent the phase separation and crystallization during the activation annealing. The NH3 treatment temperature above 700°C is necessary to suppress the boron penetration during the activation annealing at 1050°C for 1 sec in p-channel field effect transistor (p-FET). Equivalent oxide thickness (EOT) of 1.37 nm was achieved for HfSiON· (3nm)/SiO2(0.5nm) gate stack using poly-Si electrode. High effective mobility of 271/62 cm2/Vs (n/p at 0.8 MV/cm) was obtained.

Sc2O3 and MgO have been previously shown to be promising gate dielectrics for III-nitride devices. However, even though the films are initially epitaxial, they possess large numbers of defects due to the large mismatch with GaN. Thus further improvements in interface electrical characteristics will require a reduction in the interfacial mismatch between the oxides and the GaN. This paper discusses the feasibility of reducing the Sc2O3 lattice constant via the introduction of Mg and in particular investigates the relationship between growth parameters and microstructure for the resulting ScMgO alloy. Increasing the magnesium cell temperature was found to increase the growth rate but have little effect on surface roughness. Higher Mg cell temperatures also produced evidence in x-ray diffraction (XRD) of a second phase of MgScO which has the rock salt crystal structure and contains ∼2%Sc. Increasing the substrate temperature from 100°C to 300°C was found to have little effect on the growth rate and dramatically increased surface roughness. However higher substrate temperature combined with a lower Mg cell temperature produced a more uniform oxygen profile as determined by depth profiling Auger Electron Spectroscopy (AES). From AES and XRD, the solid solubility limit for ScxMg1−xO with the Bixbyite structure was reached at about XMg =0.28

High purity lanthanum oxide and praseodymium oxide thin films (C< 1 at.-%) have been deposited by liquid injection MOCVD using the volatile alkoxide precursos [La(mmp)3] and [Pr(mmp)3] in toluene-solution (mmp = OCMe2CH2OMe). 1H NMR solution studies have shown that the addition of donor species, such as tetraglyme (CH3O(CH2CH2O)4CH3) or mmpH prevent molecular aggregation and help stabilise the precursors.

We have investigated the flat-band voltage (VFB) shifts of tantalum nitride gate MOS capacitors prepared by two methods. One is CVD-tantalum nitride (CVD-TaN) deposited by the chemical vapor deposition technique using Ta[NC(CH3)2C2H5][N(CH3)2]3 as a precursor, and the other one is sputtered tantalum nitride (sp-TaN) electrodes deposited by reactive DC magnetron sputtering. In the case of the CVD-TaN electrodes, the effective work function estimated from the relationship between VFB and the equivalent oxide thickness (EOT) of the MOS capacitors was about 4.4eV after post metallization annealing (PMA) at 400°C, and shifted to the mid-gap after PMA at 950°C. Moreover, the VFB values of MOS capacitors with sp-TaN electrodes also showed the same behavior after PMA. This shift is mainly dependent on the PMA temperature, regardless of the deposition method used. Similar VFB shifts induced by PMA were also observed in sp-TaN/ Al2O3/ SiO2/ p-Si and sp-TaN/ TaOx/ SiO2/ p-Si capacitors. However, in the case of the sp-TaN/ TaOx/ SiO2/ p-Si capacitors, the VFB shift was also observed when the PDA temperature after the TaOx deposition was 800°C and the PMA temperature after the TaN deposition was only 400°C. These results strongly suggest that this VFB shift caused by the PMA originates from a thin interfacial oxide layer between the TaN gate electrode and the dielectrics. Therefore, the maximum processing temperature after gate electrode deposition is important in order to control the threshold voltage of tantalum nitride gate MOSFETs.