The formation of ultra-shallow junctions (USJs) for future integrated circuit technologies requires preamorphization and high dose boron doping to achieve high activation levels and abrupt profiles. To achieve the challenging targets set out in the semiconductor roadmap, it is crucial to reach a much better understanding of the basic physical processes taking place during USJ processing. In this paper we review current understanding of dopant-defect interactions during thermal processing of device structures – interactions which are at the heart of the dopant diffusion and activation anomalies seen in USJs. First, we recall the formation and thermal evolution of End of Range (EOR) defects upon annealing of preamorphized implants (PAI). It is shown that various types of extended defect can be formed: clusters, {113} defects and dislocation loops. During annealing, these defects exchange Si interstitial atoms and evolve following an Ostwald ripening mechanism. We review progress in developing models based on these concepts, which can accurately predict EOR defect evolution and interstitial transport between the defect layer and the surface. Based on this physically based defect modelling approach, combined with fully coupled multi-stream modelling of dopant diffusion, one can perform highly predictive simulations of boron diffusion and de/re-activation in Ge-PAI boron USJs. Agreement between simulations and experimental data is found over a wide range of experimental conditions, clearly indicating that the driving mechanism that degrades boron junction depth and activation is the dissolution of the interstitial defect band. Finally, we briefly outline some promising methods, such as co-implants and/or vacancy engineering, for further down-scaling of source-drain resistance and junction depth.

Boron implantation into preamorphized Si, followed by low temperature solid phase epitaxial (SPE) regrowth produces high activation combined with low diffusion. However, in the presence of high B concentrations, the activation obtained after the SPE regrowth only can reach concentrations in the order of a few times 1020 cm−3, and even more deactivation occurs during additional annealing. We have analyzed the role of the Si interstitials injected from the end of range (EOR) damage in B deactivation and reactivation by atomistic simulations. We have shown that the B cluster evolution can be clearly correlated to the evolution of Si interstitial defects at EOR. This is also compatible with B cluster stabilization in the presence of excess Si interstitials, observed in oxidation experiments.

Stress is known to affect the regrowth velocities during recrystallization of an amorphous layer. This study investigates how the stress from patterned structures alters regrowth and in turn affects defect formation. Prior to patterning, 80Å SiO2 and 1540Å of silicon nitride were deposited on a 200 mm [001] silicon wafer. A 40keV Si+ amorphizing implant at a dose of 1×1015 atoms/cm2 was then performed into the patterned wafer. The regrowth of the amorphous layer along the mask edge was studied by partially recrystallizing the layer for various times at 550°C both with the mask present and after etching off the oxide and nitride pads. A significant number of cross-sectional Transmission Electron Microscopy (TEM) samples were prepared and imaged. It was found that the stress from the patterned structures enhances the vertical and lateral regrowth velocities, as well as alters the shape of the amorphous-crystalline interface during regrowth. Previous studies have shown that uniaxial tensile stress increases the regrowth velocity. Simulations show that the region of interest in these samples is under tensile stresses, suggesting that this type of stress should accelerate the regrowth velocity. In addition dislocation half loops are observed to form along the mask edge for certain structures. The nucleation of these defects is suppressed by the presence of the film. The relationship between the stress from the patterned structures, the regrowth of the amorphous layer, and the formation of dislocation half-loops along the mask edge will be discussed.

The interfacial reaction between 10 nm Ni(Pt ∼0, 5, 10 at.%) and (100) Si0.75Ge0.25 substrate after rapid thermal annealing between 400 and 800°C has been studied in detail using Micro- Raman spectroscopy. Only monogermanosilicide phase was detected in the temperature range investigated. The evolution of a broad Ni(Pt)SiGe Raman peak into two distinct peaks with increasing annealing temperature is attributed to a Ge out-diffusion from the germanosilicide grains. In addition, Raman spectroscopy further proves that depletion of Ge concentration in the Ni(Pt)SiGe grains reduces at higher temperature by the addition of Pt. The above phenomena were further supported by X-ray diffraction method.

The simulation of laser annealing, applied to the formation of ultra-shallow junctions in Si, is discussed. Our effort is developing tools capable to aid the process integration issue. The numerical approach deals with a double problem: 1) the interaction between the irradiated transistor structure and the laser light, 2) the non-equilibrium evolution of the thermal field, molten regions and dopant density. Here we present a complete methodology: the calculated heat source distribution, induced by the irradiation, is used as input of a phase-field approach for the simulation of the thermal phase and impurity fields. We solved numerically the phase field equations in two dimensional structures, considering as an initial status the generic material modification due to an ion implant process. We present various simulation results obtained in MOS structures with different geometry. With the support of the simulation results we discuss the problematic and the perspectives of the excimer laser annealing process application in the fabrication of MOS devices.

An experimental study on In implantation in Si was performed, considering some factors that affect its electrical activation. One of the critical issues concerning In is represented by its outdiffusion, during the post-implantation annealing, a limiting factor to get active In concentration suitable for applications in microelectronics. The use of different thermal processes was evaluated, aimed to achieve a reduction of the outdiffusion and an increase of the electrical activation of In in silicon. The influence of the substrate purity on the electrical activation was shown to be of great importance: in particular, it was shown that C., present in the silicon substrate as a contaminant or as a co-implanted species, has a key-role in the electrical activation and diffusion of In in silicon. Furthermore, for the first time at our knowledge, the behaviour of In implanted in Si1−xGex layers grown by CVD on Si wafers was investigated, for Ge concentration of 0.5% and 1%. An enhancement in the electrical activation was observed with increasing the Ge content in the alloy.