We present state-of-the-art thin-film transistors (TFTs) incorporating amorphous silicon i-layers deposited by hot-wire chemical vapor deposition. The TFTs are deposited on glow-discharge silicon nitride as well as on thermally-grown silicon dioxide. The devices on silicon nitride have a field-effect mobility above 0.7 cm2/Vs, a threshold voltage around 2 V and a sub-threshold slope as low as 0.5 V/dec. As commonly observed, the TFTs on silicon-dioxide have higher values for the threshold voltage and the sub-threshold slope. In the annealed state the hot-wire TFTs show almost the same properties as TFTs deposited by conventional plasma-enhanced chemical vapor deposition. Nevertheless, the stress-time dependent behavior under prolonged gate-voltage stress at elevated temperature is different from that of the glow-discharge devices. The hot-wire TFTs are clearly more stable than their glow-discharge counterparts. Furthermore, we found differences in the stress behavior of the hot-wire TFTs deposited on silicon nitride and silicon dioxide.

We fabricated top gate TFTs of microcrystalline silicon (μc-Si) deposited at 360 °C. The TFTs have field-effect electron mobilities of up to 7.9 cm2/Vs in the saturation regime and 5.8 cm2/Vs in the linear regime. The highest ION/IOFF ratio is 105. Typical values for Vth is 6.5 V and for the subthreshold slope is 1.7 V/decade. The μc-Si is grown by PE-CVD from a source gas mixture of SiH4, SiF4 and H2, with a typical flow ratio of 1:20:200, at a pressure of 120 Pa and a power density of 160 mW/cm2. The TFT structure is built on un-passivated Coming 7059 glass, with 300 n+ μc-Si, 60 nm n+ μc-Si source and drain contact layers, 200 nm SiO2 or 300 nm SiNx gate insulator, and 100 nm Al gate, source and drain electrodes.

The transient response of a-Si:H thin film transistors (TFT) provides information about gap states in the channel and about the TFT conduction mechanisms. We present results of a detailed parametric study of transient leakage currents in TFTs, extending from 10-3 sec to >100 sec and at temperatures up to 400K. The form of the transient decay depends most notably on the off-state gate voltage, which determines the leakage current mechanism and magnitude. The measurements use chains of many TFTs, such that we can measure dc on/off ratios of >1011.

In the sub-threshold region (e.g. Vg~-2V) some samples exhibit non-monotonic decay of the drain current, with a minimum followed by a slow increase to a steady state. Typically this effect is barely visible at room temperature due to the extremely low values of the dc current. Higher temperatures enhance the phenomenon, which has activation energy of about 1 eV for the current magnitude and time constant. We attribute the effect to back-channel electron conduction. This explanation is consistent with the form of the TFT transfer characteristics, and the weak drain-source voltage dependence excludes a contact injection mechanism.

At more negative gate off-state voltages, some samples exhibit increasing leakage currents, indicative of hole conduction. These samples feature a monotonically decreasing transient decay with a pronounced drain-source voltage dependence, consistent with contact injection being enhanced by a hole-enriched channel in the high field drain region.

Effects of on-state gate pulse width and amplitude are also discussed, as well as the effect of high temperature stress on the TFT transients.

Self-aligned structures for bottom-gate amorphous Si TFTs provide a number of advantages, including reduced parasitic capacitance, smaller device dimensions, and improved uniformity in device performance for large-area electronics. A difficult challenge in making self-aligned TFT structures is the necessity of making source/drain contacts that exhibit low contact resistances and that are precisely aligned relative to the gate electrode. In this article, we describe a novel process for fabricating self-aligned amorphous Si TFTs. This process utilizes a pulsed excimer laser (308 nm) to dope or to activate dopants in a-Si to form the source/drain contacts. An important feature of the device design is an optical filter to protect the a-Si channel region from radiation damage during the 308 nm laser process. However, the optical filter allows the transmission of the uv light for lithography exposure from the backside of the substrate to align the channel region with the gate electrode. This new process enables the fabrication of high performance self-aligned a-Si TFTs with poly-Si source and drain contacts.

This study reports on the fabrication of inverted gate TFT devices and circuits using a low temperature microcrystalline silicon deposition process compatible with polyimide substrates. Results from the electrical and material characterization of μ-Si:H based TFT's are presented. Device performance is compared with that of α-Si:H based TFT's constructed on polyimide. Results indicate that the anticipated improvement in device performance due to an increase in the α-Si:H Hall mobility (~10 cm2/V-sec) over that of α-Si:H (~1 cm2/V-sec) is not realized. Properties of μ-Si:H films are related to deposition parameters.

A novel method to control the recrystallization depth of amorphous silicon (a-Si) film during the excimer laser annealing (ELA) is proposed in order to preserve a-Si that is useful for fabrication of poly-Si TFT with a-Si offset in the channel. A XeCl excimer laser beam is irradiated on a triple film structure of a-Si thin native silicon oxide (~20Å)/thick a-Si layer. Only the upper a-Si film is recrystallized by the laser beam irradiation, whereas the lower thick a-Si film remains amorphous because the thin native silicon oxide layer stops the grain growth of the poly-crystalline silicon (poly-Si). So that the thin oxide film sharply divides the upper poly-Si from the lower a-Si.

We report a novel TFT structure where the gate metal is embedded into a SiNx passivation layer. This allows the subsequent gate dielectric layer to be much thinner than in conventional bottom-gate structures. thereby reducing the threshold voltage and the sub-threshold slope. TFTs employing these damascene-gate structures were fabricated with SiNX gate dielectrics as thin as 50 nm. Such devices exhibit threshold voltages of 0.9 V, sub-threshold slopes of 0.1 V/dec, ION/IOFF current ratios of 106 and linear region field-effect mobilities of 0.6 cm2/Vs.

A flexible amorphous silicon (a-Si) based photovoltaic (PV) module has been developed. The a-Si solar cell fabricated on a heat-resistance plastic film with a thickness of 50μm has a new monolithic series-connected structure named SCAF to obtain a high output voltage required for practical use. Applying a-Si/a-SiGe double-junction structure to 40cm × 80cm SCAF solar cells, we obtained a stabilized efficiency of 9% with an excellent reproducibility. Flexible PV modules fabricated from the SCAF solar cells have been tested in several demonstration sites to study their durability under outdoor conditions.

We developed a novel temporary-superstrate concept for SnO2/p-i-n amorphous silicon solar cells. This concept combines roll-to-roll manufacturability, the utilization of light scattering, the conductive properties of SnO2:F, and the possibility of monolithic series connection. To this purpose, the deposition of high quality textured SnO2:F layers on aluminum foil has been developed using APCVD. Layers have been obtained with a transmission of 80 % and a sheet resistance of 12 Ω/□. After definition of the entire p-i-n cell structure including the back contact, the cell is laminated with a permanent carrier foil. By removing the aluminum foil, light can enter the cell through the textured TCO layer. A wide variety of transparent encapsulants can be used to finalize the (flexible or preshaped) product. Preliminary cells made according to this scheme have an efficiency of 6 %.

A rotating-compensator multichannel ellipsometer has been used to measure the four spectra (1.4-4.0 eV) that describe the Stokes vector of the light beam reflected from the surface of an amorphous silicon (a-Si:H) p-i-n solar cell during fabrication on textured tin-oxide (SnO2) coated glass. The Stokes vector elements include the irradiance in the reflected beam (or the reflectance) and the parameters {(Q, χ), p} of the reflected beam, where Q and χ are the tilt and ellipticity angles of the polarization ellipse and p is the degree of polarization. The value of p deviates from unity in part due to the non-uniform nature of the textured SnO2 substrate film. An analysis of Q and χ that neglects the effects of the texture can provide the time evolution of the thicknesses, microscopic structure, and the optical properties of the component layers of the a-Si:H solar cell. Deviations of the measured reflectance spectra from those predicted on the basis of the (Q, χ) analysis provide the thickness dependence of the scattering and the evolution of the macroscopic structure of the solar cell. The measurement and analysis approach is important because of its potential application for real time monitoring of solar cell production. The analysis results also provide realistic inputs for optical modeling of the effects of texture in light trapping for solar cell efficiency enhancement.

The effect of interface roughness on the optical properties of amorphous silicon (a-Si:H) solar cells was investigated using rms roughness measurements and computer modeling. We deposited four single junction a-Si:H solar cells on Asahi U type substrate each with a different intrinsic layer thickness. The roughness of the substrate and of the subsequent interfaces of the cells was measured by Atomic Force Microscopy. The relations between the computer input parameters, which describe the diffuse part of reflected and transmitted light at a rough interface, and the rms roughness of the interfaces in a-Si:H solar cell are presented. After obtaining a good matching between the simulated and measured external quantum efficiencies (QE) of the four cells, we investigated the effect of interface roughness on the absorption in all individual layers of the a-Si:H solar cell using the determined scattering parameters.

The rms roughness of the Asahi U-type substrate surface is determined to be 40 nm. Deposition of a 9 nm thick p-type a-SiC:H layer on the substrate has not changed the surface roughness. Due to a high refractive index of n-type a-Si:H the back contact interface acts as a nearly perfect diffuser for the reflected light when the rms roughness of the interface is higher than 25 nm. The rms roughness of the back interface of the four cells is found to be dependent on the intrinsic layer thickness and is larger than 25 nm.

Microcrystalline silicon (μc-Si:H) solar cells require an effective light trapping in the near infrared (NIR) to enhance the long wavelength spectral response. For this purpose we investigated back reflectors based on texture-etched ZnO/Ag stacks prepared on glass substrates by magnetron sputtering. With decreasing sputter pressure the resulting surface texture of the glass/Ag/ZnO substrates after etching exhibits a larger feature size and root mean square roughness. The increase in feature size corresponds to an increase of diffuse reflectivity. Applied in microcrystalline solar cells prepared by VHF plasma enhanced chemical vapour deposition (PECVD), the reflectors showing the largest feature size (prepared at the lowest possible sputter pressure) yielded the highest long wavelength spectral response. The μc-Si n-i-p cells prepared on the latter back reflector exhibited efficiencies of 6.9 % (short circuit current density jsc= 18.8 mA/cm2) and 7.5 % (jsc=25 mA/cm2) for an i-layer thickness of 1 μm and 3.5 μm, respectively.

A method is presented to characterize the TCO/p contact and the TCO sheet resistance in a-Si based p-i-n superstrate devices. It requires having scribed TCO strips, which are electrically isolated before a-Si deposition, then fabricating rows of individual devices on each strip. Analysis of 4-terminal measurements in different V-sensing configurations yields the TCO/p contact and TCO sheet resistance in a straightforward manner. The method is applied to devices fabricated on 3 brands of commercial SnO2 substrates. The TCO/p contact resistance is found to be ~2 Ω-cm2 and the sheet resistance decreases by 2-4 Ω/sq after a-Si deposition on all 3 brands of SnO2 substrates.

A systematic approach has been used to scale up high efficiency 0.25cm2 active-area amorphous Si alloy based triple-junction devices to high-efficiency encapsulated modules of aperture area ~920cm2. In order to analyze the losses involved in the scale-up, intermediate aperture area, 40cm2 and 450cm2, modules have also been fabricated. The best stable active-area efficiency obtained on the small-area cells is 12.9%. The best initial efficiency of a ~920cm2 aperture area encapsulated module is 12.1%. National Renewable Energy Laboratory (NREL) has independently light soaked three of the ~920cm2 modules. They have measured a stable efficiency of 10.5% which represents a new world record. This paper presents various aspects of the large-area module work.

Our investigations study the influence of various deposition parameters on the structural and optoelectronic properties of a-Si:H deposited at temperatures of 100 °C and below. Despite a significant material quality deterioration at low substrate temperatures, we observe remarkable improvements of charge carrier transport properties due to an increased H2-dilution of the process gases. In case of doped layers, we restore the electrical conductivity of low temperature n-type a-Si:H to standard values, whereas the p-layer quality is still inferior. We incorporate our optimized low temperature layers into a variety of solar cell types, including single and tandem cell structures. In addition to our conventional pin-structures we also successfully develop nip-cells for growth on opaque polymer substrates. From pinpin tandem cells, we record initial efficiencies of 6.0 % at a deposition temperature of 100 °C and 3.8 % at 75 °C. Interestingly, our nipnip tandem structures attain similar values which offers the possibility for deposition on low-cost plastic substrates. The mechanical flexibility of such substrates offers a wide variety of novel applications.

We describe applications of PV Optics to analyze the behavior of a metallic back-reflector on an a-Si solar cell. The calculated results from PV Optics agree well with the measured data on solar cells. Several unexpected results obtained from these calculations are qualitatively explained.

This paper discusses material requirements for junction layers needed to obtain solar cells with highest possible open-circuit voltages (VOC). In a typical a-Si:H-based “p/i/n” solar cell, this includes the transparent conductive oxide (TCO) contact layer, the p-layer, a “buffer layer” inserted at the p/i interface, and the surface portion of the intrinsic layer. In HIT-cells, the i-layer between (n-type) c-Si and (p-type) a-Si:H may be regarded as the buffer. Our suggestion to obtain high values of VOC relies on using materials with high lifetimes and low carrier mobilities that are capable of reducing surface or junction recombination by reducing the flow of carriers into this loss-pathway. We provide a general calculation that supports these approaches and can explain why these schemes are beneficial for all solar cells.

Several promising new methods for amorphous silicon solar cell preparation involve high substrate temperatures and/or very reactive atmospheres. When incorporated into solar cells, the performance of these layers has often been less than expected due to enhanced diffusion and/or chemical reactions. This poor performance results from the harsh deposition environments. Deleterious effects include darken of TCO coated glass substrates due to hydrogen diffusion to and hydrogen reduction at the TCO interface when solar cells are prepared in the p-i-n deposition sequence. Alternatively, the deposition of TCO layers onto amorphous layers also involves rather harsh oxidizing conditions that have a deleterious effect on the top most amorphous silicon-based p-layers. Strategic use of blocking layers results in remarkably improved solar cell performance. A thin Cr layer (probably becoming Cr2O3) shows ability to improve the performance of both n-ip and p-i-n solar cells by inhibiting both O and H diffusion.

Computer simulations are reported of hydrogenated amorphous silicon germanium (a-SiGe:H) layers that make up the graded part of the intrinsic layer near the interfaces of a-SiGe:H solar cells. Therefore the graded part is approached with a ‘staircase’ bandgap profile, consisting of three layers within which the material properties are constant. Calibrated model parameters are obtained by matching simulation results of material properties of intrinsic a-SiGe:H single layers to measurements. Using the obtained model parameter sets subsequent simulations of p-i-n devices with intrinsic material similar to the single layers are matched to measured current-voltage characteristics. The changes in parameter values are evaluated as a function of optical gap.

In high efficiency narrow bandgap (NBG) a-SiGe solar cells, thin buffer layers of unalloyed hydrogenated amorphous silicon (a-Si) are usually used at the interfaces between the a-SiGe intrinsic layer and the doped layers. We investigated the effect of inserting additional a-SiGe interface layers between these a-Si buffer layers and the a-SiGe absorber layer. We found that such additional interface layers increase solar cell VOC and FF sizably, most likely due to the reduction or elimination of the abrupt bandgap discontinuity between the a-SiGe absorber layer and the a-Si buffer layers. With these improved narrow bandgap solar cells incorporated into the fabrication of triple-junction a-Si based solar cells, we obtained triple cells with initial efficiency of 10.6%.