In this paper, a 10 W ultra-broadband GaN power amplifier (PA) is designed, fabricated, and tested. The suggested design technique provides a more accurate starting point for matching network synthesis and better prediction of achievable circuit performance. A negative-image model was used to fit the extracted optimum impedances based on source-/load-pull technique and multi-section impedance matching networks were designed. The implemented amplifier presents an excellent broadband performance, resulting in a gain of 8.5 ± 0.5 dB, saturated output power of ≥10 W, and power added efficiency (PAE) of ≥23% over the whole bandwidth. The linearity performance has also been characterized. An output third-order intercept point (OIP3) of ≥45 dBm was extracted based on a two-tone measurement technique in the operating bandwidth with different frequency spacing values. The memory effect based on AM/AM and AM/PM conversions was also characterized using a modulated WiMAX signal of 10 MHz bandwidth at 5.8 GHz. Furthermore, a broadband Wilkinson combiner was designed for the same bandwidth with very low loss to extend the overall output power. Excellent agreement between simulated and measured PA performances was also achieved.

In this work we assess the feasibility of fabricating a matrix of antennas for the millimeter (mm)-wave band using the “Multi Chip Module – Deposited (MCM-D)” process. The main focus of the design is to minimize the cross coupling between the antennas fabricated on the common substrate. We investigate the use of a virtual cavity formed by metalized vias in order to reduce the cross coupling to the neighboring cells. The radiation efficiency is analyzed in detail, and experimental results of a 2 × 2 array are presented.

This paper focuses on multi-radio front-end transmitter, a function implied by cognitive radio (0.5–6 GHz). S and C bands standards (wireless local and metropolitan area networks) present a challenge, due to the signal modulation schemes (orthogonal frequency division multiplex (OFDM)/WCDMA, wideband code division multiple access) dynamic (tens of dBs), driving us to a mandatory transmitter linearization. The idea is to provide frequency, flexibility, and average power control of a multi-radio high-efficiency front end for such signals (polar/envelope elimination and restoration (EER) structure). The study implies antennas design and average power control demonstration. Based on a switched mode power amplifier (PA), a discrete detuning is possible to adapt the PA at both “WiMAX” and “Wifi5” frequencies. This architecture amplifies signals with amplitude information. This is coded here by the ΣΔ/PWM (pulse width modulation) technique, to present a constant envelope signal. The amplitude information is restored by a pass-band radio frequency (RF) filter. The antenna can be designed with a notch, to reduce the filtering constraints (selectivity and standards coexistences) and to help in the restoration of amplitude information. Average power control is illustrated by voltage supply variation and results are a possible dynamic of 9.5 dB. To complete the analysis, the simulation of the propagation channel, including antennas, with CST (free space, line of sight) is imported under AGILENT-ADS.

The electrical modeling of power packages is a major issue for designers of high-efficiency hybrid power amplifiers. This paper reports the synthesis and the modeling of a packaged Gallium nitride (GaN) High electron mobility transistor (HEMT) associating a nonlinear model of the GaN HEMT die with an equivalent circuit model of the package. The extraction procedure is based on multi-bias S-parameter measurements of both packaged and unpackaged (on-wafer) configurations. Two different designs of 20 W packaged GaN HEMTs illustrate the modeling approach that is validated by time-domain load-pull measurements in S-band. The advantage of the electrical modeling dedicated to packaged GaN HEMTs is to enable a die-package co-design for power matching. Internal matching elements such as Metal oxide semiconductor (MOS) capacitors, Monolithic microwave integrated circuits (MMICs), and bond wires can be separately modeled to ensure an efficient optimization of the package for high power Radio frequency (RF) applications.

This article aims to provide readers with a physical understanding of the propagation channel that is complementary to mathematical channel modeling. It presents an analysis of the directional propagation channel based on radiophotos. Radiophotos are graphical objects where directions of arrival are superimposed on three-dimensional (3D) panoramic photographs. The interaction between electro magnetic waves and the environment is immediately identified with these representations. This paper focuses on the direction of arrival at mobile in an urban macrocell environment. The first radiophoto collection illustrates the major propagation phenomena such as reflection, diffraction, or street canyoning. The second collection illustrates typical propagation channel profiles that are classified according to delay, azimuth, and elevation spread values. The paper also describes an original panorama-based method for estimating noise level in the azimuth–elevation domain.

Two frequency-tripler monolithic microwave integrated circuits (MMICs) reaching sub-millimeter-wave output frequencies of 315 GHz are presented. The convenient integration of transistor–based field effect transistor (FET) frequency multipliers into multifunctional MMICs is shown by integration of a single–stage frequency-tripler with a buffer amplifier generating −0.5 dBm of peak output power at 288. Without post-amplification an average output power of −10.1 dBm in the output frequency range from 285 to 315 is measured with 10 dBm of input power. The 3-dB bandwidth is more than 30 GHz and could not be determined exactly due to the measurement setup. Both MMICs are realized in a 50 nm metamorphic high electron mobility transistor (HEMT) transistor technology. A multiple power-meter measurement technique including a waveguide filter is used to measure accurately the second harmonic power content within the output spectrum.

A systematic comparison between several pairs of contact materials based on an innovative methodology early developed at NOVA MEMS is hereby presented. The technique exploits a commercial nanoindenter coupled with electrical measurements, and test vehicles specially designed to investigate the underlying physics driving the surface-related failure modes. The study provides a comprehensive understanding of micro-contact behavior with respect to the impact of low-to-medium levels of electrical current. The decrease of the contact resistance, when the contact force increases, is measured for contact pairs of soft material (Au/Au contact), harder materials (Ru/Ru and Rh/Rh contacts), and mixed configuration (Au/Ru and Au/Ni contacts). The contact temperatures have been calculated and compared with the theoretical values of softening temperature for each couple of contact materials. No softening behavior has been observed for mixed contact at the theoretical softening temperature of both materials. The enhanced resilience of the bimetallic contacts Au/Ru and Au/Ni is demonstrated.

The design of high speed integrated circuits heavily relies on circuit simulation and requires compact transistor models. This paper presents a non-linear electro-thermal model of SiGe heterojunction-bipolar transistor (HBT). The non-linear model presented in this paper uses a hybrid π topology and it is extracted using IV and S-parameter measurements. The thermal sub-circuit is extracted using low-frequency S-parameter measurements. The model extraction procedure is described in detail. It is applied here to the modeling of npn SiGe HBTs. The proposed non-linear electro-thermal model is expected to be used for the design of high-speed electronic functions such as broadband analog digital converters in which both electrical and thermal aspects are engaged. The main focus and contribution of this paper stands in the fact that the proposed non-linear model covers wideband-frequency range (up to 65 GHz).

Angle of arrival (AOA), time of arrival (TOA), and frequency of arrival (FOA) can be measured for a signal from multiple platforms. By combining such measurements it is possible to obtain high-accuracy emitter position estimates. This requires a data link with low latency and sufficient data-rate, and synchronization of the platforms in space, time, and search pattern. Typically several of the platforms will have to make their measurements in the radar sidelobes that require very high receiver sensitivity. This paper focuses on discussing how the sensitivity can be improved using antenna gain or signal processing.

The paper presents the idea of the application of passive radar on board of an airplane. The aim of the passive coherent location (PCL) system is to provide surveillance information to the pilot (or autopilot), to detect the targets in the surveillance space, and to protect the platform from collisions and other threats. The PCL system can use the available emitters of opportunity, mainly digital terrestrial TV (DVB-T) transmitters. Other sources of illuminations, such as analogue (FM) or digital radio (DAB) can be used as well.

This paper presents the design of an eight-element 60 GHz phased-array receiver chip with interference mitigation capability, fabricated in 0.25 μm SiGe BiCMOS technology. Each receiver element contains a low noise amplifier (LNA) and a vector-modulator that supports high-resolution amplitude and phase control. A fully differential power combining network follows the eight elements. The chip also includes an active power divider, a down conversion mixer, and fully integrated 48 GHz PLL to demonstrate the IF down-conversion. With LNA, a phase shifter and hybrid active and passive power combining network, each receiver path achieves 18 dB of gain, 360° phase shift in steps less than 3°, 20 dB amplitude control, and 4 GHz 3 dB-bandwidth and input referred 1 dB compression point P1 dB of each element is of −22 dBm. Each receiver element dissipates in total 132 mW. The phased-array receiver shows more than 25 dB of signal to interference noise ratio, by means of amplitude and phase control.

This paper presents two feeding techniques for the radiation characterization of integrated antennas at millimeter-wave frequencies. The first method involves feeding the antenna-under-test (AUT) with a radiofrequency (RF) probe. We compare the measurements obtained with a standard RF probe, an extended probe, and an extended probe with reversed connector orientation. We find that the reversed orientation probe produces the best results in terms of effective measurement angular sector and reduction of ripples due to diffraction. The second method involves feeding the AUT through a flexible transmission line. This method achieves a larger range of measurement angles, but still suffers from parasitic scattering likely due to the mounting bracket and still need further development.

Two different topologies of radio frequency micro-electro-mechanical system (RF MEMS) series ohmic switches (cantilever and clamped–clamped beams) in coplanar waveguide (CPW) configuration have been characterized by means of DC, environmental, and RF measurements. In particular, on-wafer checks have been followed by RF test after vibration, thermal shocks, and temperature cycles. The devices have been manufactured on high resistivity silicon substrates, as building blocks to be implemented in different single-pole 4-throw (SP4 T), double-pole double-throw (DPDT) configurations, and then integrated in Low Temperature Co-fired Ceramics (LTCC) technology for the realization of large-order Clos 3D networks.

In this paper we present the design and realization of a high-power amplifier in grounded coplanar transmission line technology using AlGaN/GaN dual-gate High electron mobility transistors (HEMTs) with a gate-length of 100 nm to achieve a high gain per stage and high output power. A large-signal model was extracted for the dual-gate HEMT based on the state-space approach. For the fabricated dual-stage amplifier a continuous-wave saturatedoutput power of up to 24.8 dBm (0.84 W/mm) was measured at 63 GHz for 20 V drain bias. A small-signal gain of more than 20 dB was achieved between 56 and 65 GHz.

We present a design strategy for a buck converter, which fulfills the high dynamic requirements of efficient envelope amplifier needed by modern efficiency enhancement techniques for power amplifiers. The proposed DC–DC converter has an innovative control system, which makes it fast, robust, and resource saving. A mathematical model describes its dynamic behavior and is used to find a setup, which gives an optimal compromise between the dynamic performance and efficiency. The approach is applicable to various state-of-the-art communication standards. As an example, an envelope following (EF) power amplifier (PA) for the wideband code-division-multiple-access (W-CDMA) modulation scheme is treated. The corresponding buck converter is implemented in a monolithic chip (except the inductor and the capacitor of the output filter). The measurements with an industry standard W-CDMA PA (RMPA2265) match very well with the forecast of the model and confirm doubling of the average efficiency.

Radio frequency (RF) and microwave amplifier research has been largely focused on solid-state technology in recent years. This paper presents design and performance characterization of a 50-kW modular solid-state amplifier, operating at 505.8 MHz. It includes architecture selection and design procedures based on circuit and EM simulations for its building blocks like solid-state amplifier modules, combiners, dividers, and directional couplers. Key performance objectives such as efficiency, return loss, and amplitude/phase imbalance are discussed for this amplifier for real-time operation. This amplifier is serving as the state-of-the-art RF source in Indus-2 synchrotron radiation source. Characterization on component level as well as system level of this amplifier serves useful data for RF designers working in communication and particle accelerator fields.

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.