A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmission line on the other side. This configuration is attractive because of its design simplicity and easy fabrication. Compared with the conventional techniques that utilize capacitors and inductors instead of the shunt 90° transmission line, the proposed LO power splitter can alleviate the issue of process variation. The demodulator demonstrates an IRR lower than −40 dBc from 37.5 to 41.5 GHz. In addition, conversion gain is 1.3 ± 0.9 dB from 33 to 41 GHz with 6 dBm LO power. The total direct current power consumption is 78 mW from 1.0 V supply voltage. At the modulation scheme of 4096-QAM, the proposed demodulator demonstrates 1.7% (−35.1 dB) error vector magnitude (EVM), which is very close to the EVM measurement floor 1.6% (−36 dB) of our millimeter-wave signal analyzer.

This paper presents the prototype demonstration where an integrated transmitter circuit drives a mobile handset terminal antenna in order to provide frequency tunability and multiple input multiple output (MIMO) operation across the 0.5–4.5 GHz frequency range. The transmitter implementation incorporates on-chip weighted signal generation, i.e. amplitude and phase scaling to provide sufficient MIMO performance in the low band (700–960 MHz) and in the high band (1.5–4.5 GHz). In the transmitter, two antenna elements are used for MIMO operation in the low band and another two in the high band. The transmitter integrated circuit (IC) is fabricated in a 28 nm bulk CMOS technology with an active on-chip area of 0.2 mm$^2$. A custom antenna measurement procedure is proposed here in order to support and verify active antenna measurements with transmitter IC. A measurement procedure for the transmitter system comprising the transmitter IC and four antenna clusters is developed and discussed in comparison with traditional passive antenna measurements. The measurement results demonstrate that the transmitter IC driving the antenna clusters provides total antenna efficiency of $-6.5$ dB to $-1.5$ dB, and envelope correlation coefficient below 0.4 across the designated frequency bands. The results indicate that the implemented transmitter IC successfully tunes frequency response of the antenna clusters, and enhances the MIMO operation of such mobile antennas.

A time-domain duplexing radio frequency (RF) front-end with integrated antenna switch, power amplifier (PA), and low noise amplifier (LNA) was developed aiming for fifth-generation communication (5G) applications covering 24–28 GHz frequency range. Antenna switch utilizes pre-existing LNA input matching network together embedded with grounded shunt transistor switch to provide sufficient isolation of receive side from PA. Respectively, high impedance of off-state PA is assumed to achieve acceptable receive performance. Resulting output power is 13.6 dBm with 15 dB of peak small-signal gain at 28 GHz. Maximum average channel power was 4.8 dBm with 100 MHz 64-QAM OFDM signal within 5G adjacent channel power ratio and error vector magnitude specifications. Receive (RX) front-end achieves 5 dB noise figure at 24 GHz and 7 dB of peak gain. Performances of amplifiers degraded only by 2 dB from switch integration. The front-end dissipates 183 and 4.6 mW of power in transmit and receive mode, respectively. The simplistic design method minimizes cost both in circuit area (only 0.19 mm2) and design time making this front-end an attractive alternative in massive phased array applications using 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon on insulator process.

In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

In this work, a shorting control (SC) scheme is integrated into a complementary metal-oxide-semiconductor (CMOS) synchronous rectifier for the output voltage regulation of a wireless power supply. The rectifier is designed to operate in a parallel tuned pickup with a 500 mW output power capability for biomedical implants. Without any additional components, the proposed SC method enables the power pickup to operate with high efficiency under variable coupling conditions while maintaining the required load power to keep the output voltage constant. Desired operating conditions are achieved with increased power transfer capability at weak magnetic coupling conditions and higher power efficiency at strong coupling. A novel derivation describes the change in efficiency with SC duty ratio. Experimental validation is completed with an original custom CMOS integrated rectifier with embedded SC. It is demonstrated that the proposed SC method can increase the overall secondary pickup power transfer efficiency by 14% as the magnetic coupling increases to the stronger end.

An efficient platform of wireless power delivery through a pair of coupling coils with a fully integrated complementary metal-oxide-semiconductor (CMOS) rectifier is designed and evaluated in this paper. The research is intended for inductively powered energy harvesting application of biomedical sensor network. By making use of high-performance active diodes fulfilling almost ideal switching (zero forward voltage drop) and circuit to be provided with negative resistance, the proposed rectifier circuit is able to achieve a maximum conversion efficiency of more than 90%. This makes it ultra low-loss without any special device requiring additional manufacturing procedures, thereby featuring dramatically reduced production cost. Experimental studies with respect to all aspects of its performance including that used to emulate a truly biological tissue are given as proof of concept.

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

A polar transmitter driven by digital input signals for envelope and phase is demonstrated, using a band-switching output resonator to achieve multiband operation. A new digital pulse width modulation algorithm is also shown to partially suppress spurious signals associated with the digital input envelope signal. The transmitter consists of a current-mode class-D (CMCD) CMOS power amplifier (PA), together with a buck converter with a dead-time generator for improved efficiency. The CMCD PA is tuned by band-switching capacitors that can handle up to 9 V, and is measured to have approximately 30 dBm output power with 31–35% drain efficiency under single-tone testing. The proposed spurious signal reduction technique works to partially suppress quantization noise without increasing power consumption. Overall efficiencies of 27.1/25.6% are obtained at 30.2/28.9 dBm continuous wave (CW) output powers and 0.85/1.75 GHz carrier frequencies, respectively. Spur suppression of 9–10 dB peak is achieved when the proposed algorithm is applied with wideband code division multiple access (WCDMA) modulation.

In this work, the design of the wideband millimeter-wave power amplifier for multiband communication is presented. In order to achieve compact, simple and robust design, a differential cascade transformer-coupled topology is used. The amplifier is implemented in 90 nm low-leakage CMOS technology and achieves 3 dB bandwidth of 8 GHz (from 60 to 68 GHz) and a peak gain of 18 dB. The PO1dB is better than 5 dBm from 58 to 80 GHz, and peak output power is 11.9 dBm with 1 dB flatness from 62 to 77 GHz. The chip consumes an area of 0.25 mm2 including bond pads and DC current of 125 mA from a 2.2 V supply.

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

This paper shows the contribution of slow-wave coplanar waveguides on the performance of power amplifiers operating at millimeter-wave frequencies in CMOS-integrated technologies. These transmission lines present a quality factor Q two to three times higher than that of the conventional microstrip lines at the same characteristic impedance. To demonstrate the contribution of the slow-wave transmission lines on integrated millimeter-wave amplifiers performance, two Class-A single-stage power amplifiers (PA) operating at 60 GHz were designed in standard 40 nm CMOS technology. One of the power amplifiers incorporates only the microstrip lines, whereas slow-wave coplanar transmission lines are considered in the other one. Both amplifiers are biased in Class-A operation, drawing, respectively, 22 and 23 mA from 1.2 V supply. Compared to the power amplifier using conventional microstrip transmission lines, the one implemented with slow-wave transmission lines shows improved performances in terms of gain (5.6 dB against 3.3 dB), 1 dB output compression point (OCP1dB: 7 dBm against 5 dBm), saturated output power (Psat: >10 and 8 dBm, respectively), power-added efficiency (PAE: 16% instead of 6%), and die area without pads (Sdie: 0.059 mm2 against 0.069 mm2).

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

This paper proposes a practical approach for developing a new class of compact slow-wave coplanar waveguide (CPW) series/shunt stubs, which offer 40% reduction in size relative to a conventional design. It demonstrates that the technique using interdigitated capacitive loading can provide size and cost reductions, while also providing performance enhancements such as better return loss. The experimental prototypes presented in this paper demonstrate the validity of the design method and the ability to print interdigitated capacitors inside the center conductor of the series/shunt stubs. The principle of achieving such high-quality circuits is detailed and is also confirmed by theoretical and experimental results, which are in reasonable agreement up to at least 70 GHz. The paper also presents a family of novel topologies of slow wave bandpass filters based on the proposed capacitively loaded CPW series/shunt stubs.

In millimeter-wave CMOS circuits, a balun is useful for connecting off-chip single-end devices and on-chip differential circuits to improve noise immunity. However, an on-chip balun occupies a large chip area. To reduce the chip area required for the on-chip balun, a new rat-race balun using a rewiring technology with a wafer-level chip-size package (W-CSP) is proposed. The W-CSP balun occupies no area in a die because it is placed over integrated circuits. In the proposed balun, an S-shaped structure is adopted in order to directly connect the balun to differential GSGSG pads on a chip with a small area. The S-shaped W-CSP balun was fabricated on a silicon-on-insulator (SOI) substrate. The core area of the S-shaped rat-race balun is 480×735 µm, which is 22.4% that of a square rat-race balun. As a result of measurement, we found that the minimum insertion loss is 1.4 dB and the operating frequency ranges from 40 to 61 GHz.

The use of 130-nm CMOS for power amplifiers at 20 GHz is explored through a set of power amplifiers as well as transistor level measurements. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, and the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor-level characterization using load pull measurements on 1-mm gate width transistors yielded 148-mW/mm output power. Transistor modeling and layout for power amplifiers are also discussed. An estimate on the maximum achievable output at 20 GHz from 130-nm CMOS power amplifiers, based on findings in this paper and the literature, is finally presented.

Hybrid complementary metal oxide semiconductor (CMOS)/molecular memory devices are based on a dynamic random-access memory (DRAM) architecture, are fast, have high density, and exhibit low power consumption. These devices use a well-characterized charge storage mechanism to store information based on the intrinsic properties of molecules attached to a CMOS platform. The molecules are designed in a rational way to have known electrical properties and can be incorporated into CMOS devices with only minor modification of existing fabrication methods. Each memory element contains a monolayer of molecules (typically 100,000–1,000,000) to store charge; this process yields a structure that has many times the charge density of a typical DRAM capacitor, obviating the necessity for a trench or stacked capacitor geometry. The magnitude of voltage required to remove each electron is quantized (typically a few hundred millivolts per state), making it much easier to put molecules in a known state and to detect that state with low-power operation. Existing devices have charge retention times that are >1000 times that of semiconductors, and nonvolatile strategies based on simple modifications of existing systems are possible. All of these devices are ultimately scalable to molecular dimensions and will enable the production of memory products as small as state-of-the-art lithography will allow.