Hostname: page-component-586b7cd67f-gb8f7 Total loading time: 0 Render date: 2024-11-22T01:02:10.619Z Has data issue: false hasContentIssue false
  • English
  • Français

Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

Published online by Cambridge University Press:  08 March 2011

Michael Kraemer ,
Daniela Dragomirescu  and
Robert Plana
Michael Kraemer*
Affiliation:
CNRS; LAAS; 7 avenue du colonel Roche, F-31077 Toulouse, France. Phone: + 33 561 33 68 52. University of Toulouse; UPS, INSA, INP, ISAE; LAAS; F-31077 Toulouse, France.
Daniela Dragomirescu
Affiliation:
CNRS; LAAS; 7 avenue du colonel Roche, F-31077 Toulouse, France. Phone: + 33 561 33 68 52. University of Toulouse; UPS, INSA, INP, ISAE; LAAS; F-31077 Toulouse, France.
Robert Plana
Affiliation:
CNRS; LAAS; 7 avenue du colonel Roche, F-31077 Toulouse, France. Phone: + 33 561 33 68 52. University of Toulouse; UPS, INSA, INP, ISAE; LAAS; F-31077 Toulouse, France.
*
Corresponding author: M. Kraemer Email: [email protected]
Get access Rights & Permissions [Opens in a new window]

Abstract

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

Keywords

MMICRFIC60 GHzCMOSreceiverRXmm-wavelow-powerUMBV-band
Type
Research Article
Information
International Journal of Microwave and Wireless Technologies , Volume 3 , Special Issue 2: 60 GHz Wireless Communication Circuits and Systems , April 2011 , pp. 131 - 138
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2011

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1]Razavi, B.: A 60-GHz CMOS receiver front-end. IEEE J. Solid-State Circuits, 41 (1) (2006), 17–22.CrossRefGoogle Scholar
[2]Alldred, D.; Cousins, B.; Voinigescu, S.P.: A 1.2 V, 60-GHz radio receiver with on-chip transformers and inductors in 90-nm CMOS, in IEEE Compound Semiconductor Integrated Circuit Symp., 2006, November 2006, 51–54.CrossRefGoogle Scholar
[3]Emami, S.;Doan, C.H.; Niknejad, A.M.; Brodersen, R.W.: A highly integrated 60 GHz CMOS front-end receiver, in ISSCC 2007, 11–15 February 2007, 190–191.CrossRefGoogle Scholar
[4]Sanduleanu, M.A.T.; Long, J.R.: CMOS integrated transceivers for 60 GHz UWB communication, in IEEE Int. Conf. on Ultra-Wideband, 2007, 24–26 2007, 508–513.CrossRefGoogle Scholar
[5]Lee, J.; Huang, Y.; Chen, Y.; Lu, H.; Chang, C.: A low-power fully integrated 60 GHz transceiver system with OOK modulation and on-board antenna assembly, in ISSCC 2009, February 2009, 316–317, 317a.Google Scholar
[6]Bozzola, S. et al. : A sliding IF receiver for mm-wave WLANs in 65 nm CMOS, in IEEE Custom Integrated Circuits Conf., 2009, September 2009, 669–672.CrossRefGoogle Scholar
[7]Vecchi, F. et al. : A wideband mm-wave CMOS receiver for Gb/s communications employing interstage coupled resonators, in ISSCC 2010, 7–11 2010, 220–221.CrossRefGoogle Scholar
[8]Mitomo, T. et al. : A 60-GHz CMOS receiver front-end with frequency synthesizer. IEEE J. Solid-State Circuits, 43 (4) (2008), 1030–1037.CrossRefGoogle Scholar
[9]Chen, K.-H.; Lee, C.; Liu, S.-I.: A dual-band 61.4–63 GHz/75.5–77.5 GHz CMOS receiver in a 90 nm technology, in IEEE Symp. on VLSI Circuits, 2008, June 2008, 160–161.CrossRefGoogle Scholar
[10]Marcu, C. et al. : A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry. IEEE J. Solid-State Circuits, 44 (12) (2009), 3434–3447.CrossRefGoogle Scholar
[11]Dickson, T.O.; LaCroix, M.-A.; Boret, S.; Gloria, D.; Beerkens, R.; Voinigescu, S.P.: 30–100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits. IEEE Trans. Microw. Theories Tech., 53 (1) (2005), 123–133.CrossRefGoogle Scholar
[12]Kraemer, M.; Dragomirescu, D.; Plana, R.: Accurate electromagnetic simulation and measurement of millimeter-wave inductors in bulk CMOS technology, in 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, January 2010.CrossRefGoogle Scholar
[13]Kraemer, M.; Dragomirescu, D.; Plana, R.: A low-power high-gain LNA for the 60 GHz band in a 65 nm CMOS technology, in APMC 2009, 2009.CrossRefGoogle Scholar
[14]M Kraemer, M.; Dragomirescu, D.; Plana, R.: A high efficiency differential 60 GHz VCO in a 65 nm CMOS technology for WSN applications, in IEEE Microwave and Wireless Components Letters, accepted for publication 2011, in press.CrossRefGoogle Scholar
[15]Kraemer, M.; Ercoli, M.; Dragomirescu, D.; Plana, R.: A wideband single-balanced down-mixer for the 60 GHz band in 65 nm CMOS, in APMC 2010, 2010.Google Scholar