The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.

Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.

For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

To build a large integration of circuits on a semiconductor chip, a composite of thin film materials of extremely small dimensions is used. For example, metallic films serve as interconnectors, gates, contacts, diffusion barriers, interfacial bonds, passivation coatings and adhesive layers, and so they are making interfaces between themselves as well as to semiconductors and insulators. The compatibility between neighboring layers and the degradation of these films and their interfaces are crucial to device yield and reliability. These problems may become more serious when we reduce the device dimensions. A review of a simple silicon device will be presented in order to illustrate some of the material compatibility and degradation problems such as contact stability and electromigration. The review will not emphasize the device performance but rather the connection between the driving force and the corresponding kinetic changes in thin films.

With the continued rapid development of integrated circuits and the evolution towards higher chip component densities brought about by down–scaling of device dimensions, it is useful to assess the limits of performance of presently known device structures using current fabrication technology. The silicon gate field effect transistor is of obvious importance, since at the present limit of decreasing dimensions these devices are expected to give comparable speed and lower powerdelay products than their bipolar counterparts. The rapid developments in fabrication methods such as increases in wafer dimensions coupled with the reduction in device dimensions has led to a reduction in maximum processing temperatures. In particular, this downward trend is incompatible with the necessity to lower contact resistance given appropriate device down–scaling.

In this paper we present techniques using ion implantation and tailored impurity profiles that are compatible with low temperature ohmic contact formation. The application of these techniques to mono- and polycrystalline silicon are presented. Our results suggest that these techniques show considerable promise for semiconductor device applications. As a consequence, a production technology that optimizes the contact resistance to both gate-poly and drain and source regions is being investigated and current results will be presented.

Electron beam evaporation is used to coat a p-type silicon substrate with a thin layer of tungsten and then with alternating layers of silicon and tungsten. Bombardment of the coated substrate with As+ ions causes intermixing of the metal and silicon layers, dispersion of contaminant atoms at the interface between the first metal layer and the substrate, and implantation of arsenic atoms in the substrate. Subsequent thermal annealing produces a shallow silicide–silicon ohmic contact and simultaneously activates the implanted arsenic donors to form a shallow p–n+ junction. This technique has been used for the fabrication of mesa diodes with good junction characteristics. A simplified version, in which only a single tungsten layer is deposited on the substrate, has been used as a self–aligned process in the fabrication of metal/oxide/semiconductor field effect transistors with a polycide gate. In the transistors the silicide contacts to the source and drain regions can be made very close to the gate, reducing both the series resistance of these regions and the overall device size.

The present capability of obtaining ohmic contacts to GaAs over a range of doping levels is reviewed. Possible models of transport across the metalsemiconductor interface are discussed and contact techniques are described. The widely used Au—Ge alloyed contact is seen to have a spatially inhomogeneous interface which appears to control its contact resistance. The most satisfactory process at this time is to alloy into a previously fabricated heavily doped layer.

The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance.

The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature.

The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.

The electrical activation of dopants in the heavily doped GaAs layers of pulsedlaser-annealed Au–Ge/GaAs contacts were deduced and shown to be higher than that in bulk GaAs. The electrical activation is shown to decrease towards the GaAs surface and is used to explain the previously observed minimum in contact resistivity profiles in terms of arsenic loss during the laser annealing. These results will be shown to be consistent with observations of concentration–dependent activation in bulk GaAs.

The Au/(In–Ge) contact to GaAs was investigated to discover the metallurgical structure of the contact–GaAs interface. A variety of intermetallic phases in the form of precipitate particles or thin films were identified, and their presence was correlated with the temperature at which the contacts were fired. The possibility of predicting the structures of the fired contacts from simple metallurgical phase diagrams is discussed, and some evidence on the influence of the precipitating phases on the electrical character of the contacts is reviewed.

Gold metallization for ohmic contacts is extensively used for the fabrication of InP/In1−xGaxAsyPn1−y light-emitting and microwave devices. While the electrical properties of Au/InP and Au/In1−xGaxAsyPn1−y have been the subject of many investigations, relatively little is known about the metallurgy of contact formation and solid state reactions occurring during high temperature alloying and the subsequent device processing steps. Therefore a temperature-dependent X-ray diffraction study on Au–Inn1−xGaxAsyPn1−y interface reactions was made as a function of composition x, y.