The as-grown surfaces of 6H SiC seed crystals grown by the Lely method have been characterized by visible light microscopy and atomic force microscopy. The surfaces were then used to seed the sublimation growth of SiC at 2300°C, in 650 torr of Ar, with a gradient of 8 °C/cm. Repeated observations of the seed surface structure after predetermined intervals in the growth reactor demonstrated that transport starts at less than 2160 °C and that voids are nucleated by heterogeneous material on the original seed surface. Near these voids, the concentration of unit screw dislocations is increased and these defects migrate during growth. Screw dislocations of opposite sign act as step sources and build mesa structures around the heterogeneous material. After only 10 min at the growth temperature, micropipe/super screw dislocation complexes form in the centers of the mesas, possibly by the migration of unit dislocations to the voids.

The process conditions during SiC bulk crystal growth by physical vapor transport (PVT) are studied both theoretically and experimentally focussing on the magnitude of achievable growth rates V and possible correlations with defect formation. An increase of micropipe density with crystallization rate is observed. Growth parameters determining V are identified allowing a general non-dimensional representation of the dependencies of growth rate from kinetics, mass transport and heat transfer. It can be shown that at conventional process conditions of SiC growth by sublimation in graphite environment (5 mbar ≤p≤ 100 mbar, 2400K ≤T≤ 2600K) growth is limited by diffusion and kinetics for very short crystal lengths L and by heat transfer for geometries L> 1 mm. Including possible destabilizing effects due to constitutional supercooling an augmentation of V without deteriorating crystal quality should be conducted by stochiometry control for supression of graphitization and control of the thermal field tailoring the axial heat transfer with process time. Finally SiC growth from the liquid phase is introduced to promise a growth technique for specific SiC material as, in contrast to PVT growth, the closing of micropipes is demonstrated to be feasible.

Semiconducting SiC is expected for power devices and higher breakdown voltage of the device is required. Growth rate of epilayer by conventional CVD is about 3 μ m/h. To make a thick epilayer, more than 10 hours are needed. To minimize the growth time, we propose sublimation epitaxial method by close space technique (CST). In the CST, source ( polycrystalline 3C–SiC plate) and substrate is closely separated by spacer and source material is sublimed and transferred to the substrate in argon. Epitaxial layers with specular surface were obtained on 6H–SiC substrates at a substrate temperature around 2200 °C and growth rate was about 100 μ/h. Nitrogen-bound exciton was observed by PL measurement at 2 K in the epilayer when 3C–SiC plate with high purity was employed as the source material. Crystallinity of the epilayer was characterized by Raman spectroscopy.

We simulate the charge carrier traffic between the energy bands and the interface states in structures like Al/SiO2/6H-SiC, Al/diamond/Si and Al/SIPOS/Si to explain their high frequency capacitance-voltage behavior. The structures have in common that traditional electrical measurement techniques performed at room temperature are strongly influenced by non-equilibrium carrier conditions at the insulator-semiconductor interface. This can result in large errors in the interface data extracted from such studies when thermal equilibrium conditions are assumed. In this work, high frequency capacitance-voltage data are compared to numerical simulations which include such thermal non-equilibrium conditions to enable more accurate estimates of interface state parameters in such structures.

With the current availability of large-area 3C-SiC films, it is imperative that stable high temperature contacts be developed for high power devices. By comparing the existing data in the literature, we demonstrate that the contact behavior on each of the different polytypes of SiC will vary significantly. In particular, we demonstrate this for 6H-SiC and 3C-SiC. The interface slope parameter, S, which is a measure of the Fermi-level pinning in each system varies between 0.4–0.5 on 6H-SiC, while it is 0.6 on 3C-SiC. This implies that the barrier heights of contacts to 3C-SiC will vary more significantly with the choice of metal than for 6H-SiC.

Aluminum, nickel and tungsten were deposited on 3C-SiC films and their specific contact resistance measured using the circular TLM method. High temperature measurements (up to 400°C) were performed to determine the behavior of these contacts at operational temperatures. Aluminum was used primarily as a baseline for comparison since it melts at 660°C and cannot be used for very high temperature contacts. The specific contact resistance (ρc) for nickel at room temperature was 5 × 10−4 Ω-cm2, but increased with temperature to a value of 1.5 × 10−3 Ω-cm2 at 400°C. Tungsten had a higher room temperature × 10−3 Ω-cm2, which remained relatively constant with increasing temperature up to 400°C. This is related to the fact that there is hardly any reaction between tungsten and silicon carbide even up to 900°C, whereas nickel almost completely reacts with SiC by that temperature. Contact resistance measurements were also performed on samples that were annealed at 500°C.

Cl2-based Inductively Coupled Plamas with low additional dc self-biases(−100V) produce convenient etch rates(500–1500Å.min−1) for GaN, AIN, InN, InAiN and InGaN. A systematic study of the effects of additive gas(Ar, N2, H2), discharge composition and ICP source power and chuck power on etch rate and surface morphology has been performed. The general trends are to go through a maximum in etch rate with percent C12 in the discharge for all three mixtures, and to have an increase(decrease) in etch rate with source power(pressure). Since the etching is strongly ion-assisted, anisotropic pattern transfer is readily achieved. Maximum etch selectivities of approximately 6 for InN over the other nitrides were obtained.

With great attention now being given to the wide band gap materials for electronic and optoelectronic device applications, there is interest in using ion implantation to introduce dopants into selected regions of devices. Work on ion implantation into SiC and the III-V nitrides is reviewed, new device concepts are given, and recent results are presented. These include SiC implantations at elevated temperatures, a GaN sample implanted with Si having an electron mobility after annealing of 106 cm2/V-s, and a novel GaN np junction diode created by implantation.

We introduce for the first time a novel rapid thermal processing (RTP) unit called ZapperTM, which has recently been developed by MHI Inc. and the University of Florida for high temperature thermal processing of semiconductors. This ZapperTM unit is capable of reaching much higher temperatures (>1500 °C) than conventional tungsten-halogen lamp RTP equipment and achieving high ramp-up and ramp-down rates. We have conducted implant activation annealing studies of Si+-implanted GaN thin films (with and without an AIN encapsulation layer) using the ZapperTM unit at temperatures up to 1500 °C. The electrical property measurements of such annealed samples have led to the conclusion that high annealing temperatures and AIN encapsulation are needed for the optimum activation efficiency of Si+ implants in GaN. It has clearly been demonstrated that the ZapperTM unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide bandgap compound semiconductors that require very high processing temperatures.

This paper presents a methodology to optimize the design of different types of IGBT using TWB (TMA WorkBench). Using RSM (Response Surface Modeling) and DOE (Design of Experiment) in TWB we have developed a methodology, which can be applied to explore the impact of design modifications on the speed improvement and study the trade-off between speed, on-resistance, and breakdown voltage of IGBT. This method is a rapid and cost-effective approach for studying design alternatives. Two-dimensional simulations were used to determine the influence of technology and design parameter on device characteristics.

The user-oriented simulator POWER2D for studying the voltage handling capability of power semiconductor devices is presented. The simulation is based on the Poisson's equation solution for an arbitrary shaped 1D, 2D, and cylindrical 3D high voltage semiconductor structures. Very fast solution of the potential is obtained for a high level of applied bias, based on incomplete LU decomposition preconditioned biconjugate gradient method, and combined with a multi-damping scheme for the Newton linearization of the non-linear algebraic equations. An original algorithm is developped ensuring a very fast and automatic search of the breakdown via the ionization integrals calculus. The predicting capability of the program is illustrated for different termination techniques showing good agreement with the experiment.

The two basic package types of current IGBT modules, which evolved from opposing requirements of traction and power transmission applications, are presented. It is shown that reliability and lifetime aspects given by traction puts most stringent limitations on the choice of materials at given cost targets. The materials used today for high power packaging and the future developments of high power IGBT-packages are discussed.

Since power devices require a thick electrically active n-type silicon layer with high resistivity and a large area, their electrical characteristics are extremely sensitive to contamination. If heavy metals diffuse into the silicon wafers during the high-temperature steps, an uncontrolled increase in the leakage current and the on-state voltage can be observed. Furthermore, current filamentation and instabilities of the electrical data can occur. It turned out that the optimization of the cleaning processes, high-temperature steps and gettering treatments alone is not sufficient to avoid such effects. It is also important to avoid silicon crystal defects by proper processing. A dramatic increase in the leakage current was correlated with the appearance of silicon defects decorated with heavy metals. As a consequence of the low doping level of the n-base, the blocking voltage and the failure rate due to cosmic radiation are sensitive to contaminating atoms acting as donors.

A new methodology to optimise the design of Floating Ring (FR) termination technique for high voltage device is presented. The basic idea is to simulate the blocking capability of the structure with only one guard ring and then extend the results to a multiple FR system. A second advantage of our method is to include the ring width in the optimisation process. The effectiveness and efficiency of our methodology is illustrated by optimising a FR structure with a junction depth xj=5 μm and Si substrate doping 2.1014cm−3 A seven rings structure is optimized giving 90 % efficiency in respect to the ideal plane parallel junction breakdown voltage VBD =840 V. Moreover the 2D simulation program POWER2D has been extended by an efficient numerical algorithm to reduce drastically the number of iterations when adjusting the quasi-Fermi potential of the rings.

We modeled the breakdown voltage, critical current density and maximum operating frequency of several GaN and GaN/AlN based high power and high temperature electronic devices. Important model parameters which influence device design and performance are minority carrier recombination lifetime and critical field for electric breakdown.

GaN Schottky devices have been fabricated in the planar geometry. Current-voltage measurements indicated the importance of the vertical geometry for achieving large breakdown voltages. The minority carrier (hole) recombination lifetimes have been measured by electron beam induced currents (EBIC). The measured hole lifetime of 7 ns and estimate for the critical field indicate the possibility of GaN/AlGaN thyristor switch devices operating at 5KV with current densities approximately equal to 200 A/cm2 and at frequencies above 2MHz.

The GaN structural and optical materials quality and processing requirement for etching is discussed.

X-band performance, high temperature DC operation, and uniformity have been evaluated for 1 μm gate AlGaN/GaN HEMTs grown by RF atomic nitrogen plasma MBE. Deposition and fabrication were performed on 2-inch (0001) saphirre substrates to determine process uniformity. HEMTs with 300 μm total gate width and dual gate finger geometry have been fabricated with 650–700 cm2/V s mobility. Maximum frequency cut-offs on the order of of 8–10 were achieved. DC performance at room temperature was >500 mA/mm, and external transconductance was >70mS/mn. The transistors operated at test temperatures of 425°C.

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter-base and base-collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter-base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8V to IOV, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in DC characteristics after operation at an emitter current density of 90kA/cm2 and a collector bias, VCE, of 2V at room temperature for over 500 hours. Typical common emitter current gain was 50. An ft of 80 and fmax of 155 GHz were achieved for 2 × 4 μm2 emitter size devices.

We have succeeded in making high resistive AlxGa1−xAs by oxygen doping (AlxGa1−xAs:O) and applying them to buffer layer for power metal-semiconductor field effect transistor (MESFET). Samples of Al0.3Ga0.7As:O were prepared by metalorganic vapor phase epitaxy (MOVPE). Oxygen-related levels in A10.3Ga0.7As:O were investigated by applying isothermal capacitance transient spectroscopy (107S) to MIS (Al/Al0.3Ga0.7As:O/n-GaAs) diodes. A breakdown voltage and a two terminal gate breakdown voltage of the MESFET with the Al0.3Ga0.7As:O buffer layer became higher as increasing in the intensity of oxygen related peak in the ICTS spectra. These results indicate that the electrically active oxygen in the Al1−xGa1−xAs:O is an important factor for the device characteristics.

Secondary electron emission spectroscopy is used to investigate the generation and transport of impact-ionized electrons in wide bandgap material. Secondary electron yield and energy distribution measurements from C(100) and CVD diamond samples are analyzed to obtain information about the internal gain and electron energy distribution following impact ionization, as well as the effects of the transport process on the internal electron distribution. By studying the emission from surfaces having a negative electron affinity (NEA), the total transmitted intensity and the full energy spectrum of the internal electrons are revealed in the measurements. Energy spectra measured from the diamond samples contain a low-energy peak whose energy position and width are independent of incident beam energy. This suggests that the peak represents the electron distribution produced by impact-ionization events. A large percentage of the total emitted electrons lie within this peak, indicating that the impact-ionization process is very efficient at generating low-energy electrons. Very high yields are measured from both samples, establishing the presence of high internal gain and efficient electron transport in the material. From the linear slope of the yield curves, the escape depth of the low-energy electrons is deduced to be much larger than ˜ 0.1 μm in both diamond samples.

The development of high power devices based on silicon carbide requires a more complete understanding of the oxide formation process and interface characteristics. By using an integrated UHV system, samples were cleaned and oxides deposited in situ. The approach of the oxide formation process was to form the initial insulator, a few angstroms thick, and then deposit an oxide. Various deposition techniques are used in the oxide growth process; both thermal and plasma enhanced chemical vapor deposition were employed with two different precursors (oxygen and nitrous oxide), and the results were compared with thermal oxidation. The morphology of each of the deposited oxides was compared to the bare substrate and the thermal oxide wafers. This study focuses on the morphology of the different deposition processes using AFM. Examination of the morphology of the initial insulator growth process and the oxide deposition process gives insight into the physical characteristics of the silicon dioxide deposited on silicon carbide. The RMS values of the initial insulator formation and the control wafers are 0.93 and 0.95 nm respectively. Meanwhile, the RMS values for PECVD (200–400°C) and thermal CVD (400–600°C for oxygen-silane and 800–1000°C for nitrous oxide-silane) range from 1.43 to 1.93 nm.

GaN MIS diodes were demonstrated utilizing AIN and Ga2O3(Gd2O3) as insulators. A 345 Åof AIN was grown on the MOCVD grown n-GaN in a MOMBE system using trimethylamine alane as Al precursor and nitrogen generated from a wavemat ECR N2 plasma. For the Ga2O3(Gd2O3) growth, a multi-MBE chamber was used and a 195 Å oxide is E-beam evaporated from a single crystal source of Ga5Gd3O12. The forward breakdown voltage of AlN and Ga2O3( Gd2O3) diodes are 5V and 6V, respectively, which are significantly improved from ˜1.2 V of schottky contact. From the C-V measurements, both kinds of diodes showed good charge modulation from ccumulation to depletion at different frequencies. The insulator/GaN interface roughness and the thickness of the insulator were measured with x-ray reflectivity.