The nitride-based SONOS cell, for its excellent scalability and process simplicity, is the candidate to push the scaling roadmap for FLASH memories beyond the limit imposed on floating-gate memories by the electrostatic interference between adjacent cells. The traditional SONOS cell consists of a nitride layer (the storage element) encapsulated by two SiO2 layers which isolate the nitride layer from the Si substrate and the poly-Si gate (Poly-Si/SiO2/Si3N4/SiO2/c-Si). However, the thick tunnel oxide necessary to meet the retention requirements imposes a severe limit on the erase performance because of the erase saturation phenomenon. One possibility to guarantee both the erase and the retention performance is the replacement of the top SiO2 layer with materials of higher dielectric constant (high-k dielectric). The presence of a high-k dielectric reduces the electric field across the top dielectric, thus decreasing the unwanted parasitic electron injection from the gate during the erase operation. This will allow the cell to erase deep so to meet a basic requirement for Gigabit multilevel NAND memories. The introduction of high-k materials in the SONOS stack is unfortunately not straightforward. One problem is the Fermi-level pinning at the poly-Si/high-k interface. Another problem is the morphological changes the high-k material undergoes during the device fabrication thermal budget. These changes can modify the k-value and affect the band offset between gate and high-k material. The results may, in both cases, be the decrease of the barrier for electron injection from the gate and, as a consequence, the deterioration of the erase performance. In this paper we study the effect of gate material and of the morphological transformation associated with the high-k post deposition anneal on the erase and the retention behaviour of nitride-based cells. Two different high-k dielectrics are investigated: Al2O3 (which has already been found to be able to significantly improve the erase operation, guaranteeing at the same time excellent endurance and sufficient bake retention) and HfAlO. We show that both for Al2O3 and HfAlO a trade-off exists between erase and retention, higher PDA temperatures being beneficial for erase but detrimental for retention. We also discuss the effect of Fermi level pinning and poly-Si depletion on the erase behaviour and compare the erase performances of several PVD- and AVD-deposited metal gates.

In order to deposit conformal films in the high aspect ratio trench and via structures in future high-density phase-change memory devices, suitable ALD/CVD precursors are needed. We report on the development of novel germanium(II) metal-organic ALD/CVD precursors containing amide, cyclopentadienyl, and amidinate ligands. The physical properties, volatility, and thermal behavior of the precursors were evaluated by simultaneous thermal analysis (STA) and vapor pressure measurements. Stability studies were conducted to investigate the suitability of the precursors for use as ALD/CVD precursors for device manufacturing.

Recently, organic nonvolatile memory has attracted much interest as a candidate device for next generation nonvolatile memory because of its simple process, small device area, and high speed. To investigate electrical characteristics of small molecular organic nonvolatile memory with Ni as a middle metal layer, we developed a small molecular organic nonvolatile memory with the device structure of Aluminum tris (8-hydroxyquinolate) (Al/Alq3), Ni nanocrystals, and Alq3/Al. A high vacuum thermal deposition method was used for the device fabrication. It is critical that the fabrication process condition for Ni nanocrystals be optimized, including ∼100 Å thickness, 0.1 Å/sec-evaporation rate, and in-situ plasma oxidation for effective oxidation. The reasons we chose Ni for the middle metal layer are that Ni has a smaller grain boundary, which is beneficial for scaling down and has a larger work function (∼5.15 eV) that can make a deep quantum well in an energy band diagram, compared with that of Al. Our device showed an electrical nonvolatile memory behavior including Vth of ∼2 V, Vw (write) of ∼3.5 V, negative differential region (NDR) of 3.5∼7 V, Ve (erase) of 8 V, and symmetrical electrical behavior at reverse bias. In addition, an interesting behavior of electrical properties was that, although retention and endurance characteristics were similar to the Al device, the Ion/Ioff ratio was greater than 104 at Vr (read) of 1 V. This value of the Ni device was higher than 102 compared to that of the Al device. Also, small molecular organic nonvolatile memory with a Ni middle layer with α-NPD at same fabrication condition showed more unstable characteristics than Alq3. We can speculate that there is a relationship in fabrication condition between the middle metal material and the organic material. Finally, we conclude that our device with a Ni nanocrystals middle layer is more reliable and useful for small molecular organic nonvolatile memory.

Organic devices fabricated with a top metal layer/conductive organic layer/middle metal layer/conductive organic layer/bottom metal layer structure have been reported to demonstrate nonvolatile memory behavior such as an after writing (Ion)/after erasing (Ioff) performance of > 1 × 101 and a response time of ∼10 ns, when the organic conductive layers were AIDCN (2-amino-4, 5-imidazoledicarbonitrile), Alq3 (Aluminum tris(8-hydroxyquinoline)), or α-NPD. We fabricated an organic nonvolatile memory device with a structure of α-NPD/Al nanocrystals surrounded by Al2O3/α-NPD/Al, where α-NPD was N,N'-bis(1-naphthyl)-1,1'biphenyl4-4''diamine. A layer of Al nanocrystals, confirmed by a 1.25-MV high voltage transmission-electron-microscope, was uniformly produced between the α-NPD layers by Al layer evaporation at 1.0 Å/sec on the α-NPD followed by O2 plasma oxidation. We confirmed a conduction bistability of ∼102 and a threshold voltage for a set state of 3 V. Al nanocrystals surrounded by amorphous Al2O3 were formed in the α-NPD. They presented seven different reversible current paths for an electron charge or discharge on the nanocrystals. The current slightly increased with an applied bias from 0 V to Vth (a high resistance state (Ioff)), abruptly increased with an applied bias from Vth to Vp, decreased with an increasing applied bias from Vp to Ve (a negative differential resistance (NDR) region), and slightly increased with an applied bias above Ve. After sweeping the first applied voltage from 0 to 10 V (erase), a second applied bias was swept from 0 to Vp (program), where the current followed a high resistance state (Ioff). Next, a third applied bias was swept from 0 to Vp again, where the current followed a low resistance state (Ion). Surprisingly, the ratio of Ion to Ioff was ∼1×102, which is enough current difference to be nonvolatile memory behavior. These I-V characteristics under a positive applied bias were symmetrically repeated under a negative applied bias. All the current sweeping paths were reproducible and symmetrical for an applied bias polarity. In particular, our device demonstrated multi-level nonvolatile memory behavior. It also revealed the current conduction mechanism for each of its operation regions. We observed that the high resistance and low resistance regions followed space-charge-limited current conduction, the Vth to Vp and VNDR to Ve regions followed precisely thermionic-field-emission current conduction, and the above Ve regions followed space-charge-limited current conduction.

Switching resistance of a metal/oxide/metal structure (Pt/PrxCa1-xMnO3/Pt) upon the stimulation of electric pulse has triggered vast research interests and activities for next generation resistive RAM application. Continued from an earlier paper [1] that studied the mechanism of switching resistance, this paper extends to the switching endurance discussion using admittance spectra. Experimental data indicated that there exist interfacial dipoles (or states) at metal/oxide interfaces. Switching resistance comes from the change of interfacial dipoles. However, those interfacial dipoles are all meta-stable indicating the problem of long term switching endurance. We have tested many metal/PCMO contact combinations and characterized those contacts with basic memory criteria: bit separation, data retention, switch endurance, switching speed, and readout limitations. Among them, TiN/PCMO showed large bit separation, excellent data retention, and fast switching speed, but failed long term switching endurance test. Furthermore, the poor switch endurance is discussed using energy-well diagram. Therefore, a material system providing bi-stable states with reasonably large free energy separations is a must for this type of RRAM application. These energy levels can come from either structure or electrochemical potential differences at the metal/oxide interfaces.

Temperature dependence of electrical properties in NiO thin films for ReRAM applications has been investigated. I-V measurements have been carried out in the temperature range from 100K to 523K. The resistance in the high resistance state (HRS) is almost independent of temperature below 250K, whereas it decreases with an activation energy of 300 meV above 250K. Hopping conduction and band conduction may be dominant in the low- and high-temperature range, respectively. Admittance spectroscopy on the NiO/n+-Si structure¡¡reveals the existence of a high density of traps, which may contribute to the conduction in HRS. In the low resistance state (LRS), however, the resistance slightly increased in the whole temperature range and the trend is similar to that of metallic Ni film, indicating the metallic Ni defects is related to the conduction in LRS. The Pt/NiO/Pt structure demonstrated stable resistance switching even at temperature as high as 250°C or higher. Since other competitive nonvolatile memories will face severe difficulty in high-temperature operation, the present ReRAM shows promise for high-temperature application.

Chain-of-sphere (CoS) nanostructure containing Permalloy (Fe20Ni80) nanospheres of uniform size (d=50 nm) has been studied using micromagnetic simulation. These large-size Permalloy nanospheres support magnetic vortex structure upon relaxation. The presence of magnetic vortices in CoS architecture affects its magnetic properties significantly. Micromagnetic behaviour of Permalloy CoS system was studied focusing on the magnetization reversal process. The presence of magnetic vortices triggers a vortex creation and annihilation mechanism (VCA) involving the formation and breaking of an inversion symmetry (IS) feature. This VCA mechanism has been studied using 3D micromagnetic simulation and results of coercivity and vortex parameters are presented.

BaZrO3 (BZO) doped Sr0.8Bi2.2Ta2O9 (SBT), a new modified SBT, thin films were prepared and related ferroelectric and electrical properties were evaluated.

We present the realization of hybrid silicon core/silicon nitride shell nanodots by Low Pressure Chemical Vapor Deposition (LPCVD) and their application as floating gate in Non Volatile Memory (NVM) devices. The LPCVD process includes three steps: nucleation using SiH4, selective growth of the silicon nuclei using SiH2Cl2 and finally selective growth of silicon nitride using a mixture of SiH2Cl2 and NH3 around the silicon dot. The two first steps have already been described in literature. We will therefore focus on the selective growth of a nitride layer on silicon dots. Morphological characterization using Scanning Electron Microscopy (SEM) allows control over dots size – 5 to 10nm – and density – up to 1E12/cm2. High Resolution Transmission Electron Microscopy (HRTEM) shows a crystalline silicon core and an outer shell of amorphous silicon nitride. Energy Filtered TEM pictures confirm that the nitride layer is deposited only around the silicon dots and not on the oxide. Oxidation resistance of the silicon nitride shell is also investigated. A 2nm thick silicon nitride layer is an efficient barrier to an oxidation at 800°C in dry oxygen for 5 minutes. We thus have a very thin high quality stoechiometric nitride layer. Such a high quality nitride film can only be achieved using in-situ deposition i.e. on an oxide-free silicon surface. Finally, hybrid Si/SiN nanodots are integrated in a single memory cell with high-K interpoly dielectric. Electrical results show large threshold voltage shift of 6V. The use of silicon nitride shells on the silicon dots has therefore two main advantages: it provides both oxidation resistance and charge storage enhancement.

Single-layer devices of the structure indium-tin-oxide/polymer/aluminum were fabricated from two non-conjugated polymers with pendant carbazole groups in different spacer units. The device based on poly(2-(N-carbazolyl)ethyl methacrylate) (PMCz) exhibited non-volatile write-once-read-many-times (WORM) memory behavior with an ON/OFF current ratio up to 106, while the device based on poly(9-(2-((4-vinylbenzyl)oxy)ethyl)-9H-carbazole) (PVBCz) exhibited volatile memory behavior with an ON/OFF current ratio of approximately 103. In the absence of a spacer unit between the pendant carbazole group and the main chain, regioregular poly(N-vinylcarbazole) (PVK) exhibited only one conductivity state (ON state). The switching and memory effects observed were attributed to conformation changes of the pendant carbazole groups.

The resistance switching in Pt/Co-O/Pt and Ta/Co-O/Pt has been investigated. Compared to Pt/Co-O/Pt, the reset current was more efficiently decreased in Ta/Co-O/Pt by using the load resistor in the forming process, indicating that the embedded resistance component with little parasitic capacitance effectively limits the current in the forming process. The reset process with the reset current lower than 0.15 mA was successfully demonstrated in Ta/Co-O/Pt. In addition, the high speed resistance switching by the voltage pulse with the pulse width of 20 ns was carried out, by investigating the pulse voltage height dependence of reset speed in Ta/Co-O/Pt.