The kinetics of MBE growth of Ga1-x.,Alx,As is studied theoretically using the stochastic model of MBE growth based on the master equation approach and the random distribution approximation. The surface ordering phenomenon during the 001 growth of Ga0.5Al0.5 As is investigated as a function of the growth conditions. The atom pair interaction energy parameters for various surface configurations were obtained from the first principle calculations. The other model parameters needed in the description of the kinetic processes are obtained from the available experimental data. The ordering kinetics is studied as a function of fluxes, flux ratio and growth temperature. The degree of ordering is estimated in terms of the short range order parameter. The short range order parameter increases with temperature till 650°K and 750°K for cation to anion flux ratios 2 : 1 and 1 : 5, respectively. Beyond this critical temperature, the short range order parameter decreases. This critical temperature is identified as the kinetic order-disorder temperature. The order-disorder phenomenon observed in this theoretical study is explained in terms of the dependence of the surface migration rate of the cations on the growth temperature. The dependence on the order-disorder temperature on the flux ratio is attributed to decreased surface migration for larger flux ratios.

Materials grown at a low temperature by MBE and subsequently annealed at a high temperature have an excess amount of Arsenic and have demonstrated high dielectric breakdown strength and low carrier lifetime. These properties have found applications in analog and switching power applications, in picosecond pulse generation, in device isolation and in the selective intermixing of heterostructures. This paper reviews these applications.

MBE GaAs grown at low temperature (300°C) is evaluated for its suitability as a buffer layer for microwave power FETs. Hall effect and capacitance-voltage (C-V) measurements show that low temperature (LT) buffers may have strong deleterious effects on the electronic quality of FET active layers unless they are heat-treated in-situ at 600'C and topped with a thin (∼0. lμm) 600°C GaAs buffer prior to growth of the FET active layer. The voltage isolation properties of the LT buffers are found to be thermally stable to rapid thermal anneals up to 870°C for 10 seconds.

Transmission electron microscopy (TEM) cross-sections were examined on FET layers with LT buffer layers which ranged in thickness from 0.1μm to 1.0μm. The TEM reveals a high density (∼1017 cm−3) of small (<100Å) arsenic precipitates in all of the buffer layers studied. In cases where the LT buffer is not heat treated and topped with a thin 600°C GaAs buffer layer, dislocations and arsenic precipitates extend from the buffer layer into the FET active layer. Their presence in the active layer correlates with the degradation in electronic properties observed with Hall effect and CV. Microwave power FETs were measured at DC and 5 GHz. DC and RF results for devices with LT buffer layers are comparable to devices with conventional buffer layers.

DC characteristics of a GaAs MISFET structure using low-temperature GaAs (LTGaAs) as the gate insulator were investigated. MISFETs with different gate to channel separation (d) were fabricated. The dependence of four important device parameters such as gate-drain breakdown voltage (VBR), channel current at zero gate bias (Idss), transconductance (gm), and gate-drain turn-on voltage (Von) on the gate insulator thickness were analyzed. It was observed that (a) in terms of Idss and gin, the LT-GaAs gate insulator behaves like an undoped regular GaAs layer and (b) in terms of VBR and Von, the LT-GaAs gate insulator behaves as a trap dominated layer.

Since epilayers of GaAs grown at low substrate temperature (LTGaAs) and annealed at 600°C were first demonstrated to be an effective buffer layer for eliminating backgating effects, the material properties and electronic characteristics of bulk LTGaAs have been actively investigated. Less attention has been paid to thin layers of LTGaAs (∼2000Å), although these have been shown to improve gate-to-drain breakdown characteristics when incorporated as the surface insulator layer in GaAs MISFET's. In bulk LTGaAs that has been annealed for 10 minutes at 600°C, the formation of arsenic precipitates with a density of 1018 cm-3 has been observed. These are considered to be at least partially responsible for the high resistivity of LTGaAs2. While the exact mechanism of precipitate formation is currently unknown, it would seem reasonable to expect the availability of the growth surface to have a significant effect on any defect redistribution during the anneal. This surface effect would become increasingly apparent as the LTGaAs layer thickness was decreased. It is desirable for MISFET applications that the LTGaAs gate insulator layer be as thin as possible, whilst maintaining high breakdown, in order to maximize device transconductance. To achieve this, it is important to understand how the observed bulk features (such as ∼60Å size arsenic precipitates) are affected in thin LTGaAs layers

A model for gate breakdown in MESFETs and HEMTs is proposed. The model is based upon a combination of thermally assisted tunneling and avalanche breakdown. When thermal effects are considered it is demonstrated that the model predicts increasing drain-source breakdown as the gate electrode is biased towards pinch-off, in agreement with experimental data. The model also predicts, for the first time, the gate current versus bias behavior observed in experimental data. The model is consistent with the various reports of breakdown and light emission phenomena reported in the literature.

We present here the results of a study on the effect of substrate temperature, Ts, on the electrical and physical characteristics of low temperature (LT) molecular beam epitaxy GaAs layers. Hall measurements have been performed on the asgrown samples and on samples annealed at 610 °C and 850 °C. Si implantation into these layers has also been investigated.

The ultrafast carrier dynamics in GaAs, In0.52Al0 48As on InP, and In0.53Ga0.47As on InP, grown by molecular-beam-epitaxy (MBE) at low substrate temperatures, are investigated. A reduction in the carrier lifetime is observed with decreasing growth temperatures. The shortest carrier lifetimes of typically a picosecond (ps) are obtained at the lowest growth temperature range of 150 – 200 'C. Femtosecond optical absorption and reflectance measurements have been used to verify the sub-picosecond carrier lifetimes. Photoconductive switching measurements on these materials, measured using the technique of electro-optic sampling have further confirmed the sub-picosecond carrier lifetimes, and have also resulted in the generation of subpicosecond electrical signals. These short electrical pulses have been used for a variety of ultrafast optoelectronic applications.

A high performance, Al0.3Ga0.7As/GaAs based, optically gated thyristor with a bulk semi-insulating(SI) GaAs 650 μm in thickness as the voltage blocking layer has been fabricated and characterized for high power pulsed switching applications. Low temperature(LT) GaAs was used to passivate the device surface and was found to greatly improve the switch hold-off voltage. The switched current as a function of bias up to 2,200 V (34 kV/cm) has been tested and the maximum switched current was 240 A with a di/dt equal to 2.02×1010 A/s. The forward dynamic current-voltage characteristics have been measured and the dissipated energy per switching determined. It was found that very sensitive triggering of the switch is possible, even with a light emitting diode operating in the sub-mW range, when the thyristor is reverse biased. The sensitive triggering is a result of the carrier tunneling through the reverse biased pn junctions.

We report on the generation of 825 V electrical pulses with 1.4 ps rise time and 4 ps Full-Width-at-Half-Maximum using pulse biased Low-Temperature-grown GaAs photoconductive switch triggered by submicrojoule, 150 fs laser pulses. Dependence of the temporal pulse shape on both the electric field and the optical energy is observed and discussed.

We report on the development of a new, integrable photoconductive-type detector based on low-temperature-grown GaAs. The detector has a response time of 1.2 ps and a 3-dB bandwidth of 375 GHz. The responsivity is 0.1 A/W. This is the fastest photodetector reported to date. We discuss the unique properties of this device, including its performance as functions of both light intensity and bias voltage.

Metal-Semiconductor-Metal (MSM) photodiodes fabricated from low temperature (LT) grown GaAs by molecular beam epitaxy have been characterized for wavelengths extending out to 1.5μm. External quantum efficiencies on the order of 0.5 % have been measured for subbandgap wavelengths, which translates to internal quantum efficiencies of 2–4 % for the interdigitated electrode structure with lμm finger spacing and width. Although the effective lifetime of the LT-GaAs has been determined to be <1ps, an MSM photodiode response of ∼10ps full width at half maximum was measured by correlation techniques at 820 nm wavelength, and a system limited response of 3GHz was measured at 1.3 μm wavelength. These experimental results will be described in detail.

In this work we demonstrate that photopumped quantum wellheterostructure lasers with excellent optical quality can be grown ontop of a LT GaAs buffer layer by molecular beam epitaxy. Hightemperature thermal annealing of these lasers blue-shifts the laseremission wavelengths but the presence/absence of a LT GaAs layerhad little effect on the overall laser thresholds. Also, to first order itwas not necessary to include an AlAs barrier layer to preventadverse effects (as has been necessary in the gate stack of MESFETs to prevent carrier compensation).

We report on the characterization of Low Temperature (LT) epitaxial growth of GaAs photoconductors. Samples were characterized using electro-optic sampling, transient femtosecond reflectivity, transmission electron microscopy, and pulsed terahertz spectroscopy as a function of growth temperature, As4 flux, doping and anneal conditions. We find the strongest effect on pulsewidth to be the temperature of an ex-situ rapid thermal anneal. In addition we find evidence of a temperature threshold for As precipitation. For more than an order of magnitude change in As precipitate density we find no corresponding change in electrical pulsewidth. Doping to 1017/cm3 also produces no change in the measured electrical response.

A new structure is proposed and described which can solve the most severe drawbacks of current architectures for Josephson FETs. Its advantages are discussed, and several realizations are suggested.

AlInAs and GaInAs lattice matched to InP and grown by MBE over a temperature range of 200 to 350°C (normal growth temperature of 500°C) has been used to enhance the device performance of inverted (where the donor layer lies below the channel) High Electron Mobility Transistors (HEMTs) and Heterojunction Bipolar Transistors (HBTs), respectively. We will show that an AlInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs donor layer and GaInAs channel significantly reduces Si movement from the donor layer into the channel. This produces an inverted HEMT with a channel charge of 3.0×1012 cm−2 and mobility of 9131 cm2/V-s, as compared to the same HEMT with a spacer grown at 500 °C resulting in a channel charge of 2.3×1012 cm−2 and mobility of 4655 cm2/V-s. We will also show that a GaInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs emitter and GalnAs base of an npn HBT significantly reduces Be movement from the base into the emitter, thereby allowing higher Be base dopings (up to 1×1020 cm−3) confined to 500 Å base widths, resulting in an AlInAs/GaInAs HBT with an fmax of 73 GHz and ft of 110 GHz.

InP layers were grown on semi-insulating InP wafer by molecular beam epitaxy (MBE) at low substrate temperatures (<200° C), using solid phosphorus source. We use x-ray diffraction, double crystal x-ray rocking curve, Auger electron spectroscopy, and temperature-dependent Van der Pauw and Hall effect measurements to characterize the as-grown and annealed InP layers. It is found that the InP layer is in poly-crystal state with excess P over 7 at%. The layers became single crystal after annealing above 400°C. The resistivity of the InP layer decreased from 60 Ωcm for an as-grown sample to 0.82 Ωcm after 400°C RTA annealing. The different role of excess P as compared to the role played by excess As in LT-GaAs is discussed based on the P properties.

The introduction of GaAs grown at low MBE growth temperatures has spurred considerable activity in attempts to understand conduction mechanisms and optical properties. In LT GaAs, the formation of microscopic As precipitates dominates the conductivity, producing electronic transport mainly by variable range hopping conduction. The resulting high resistivity and short carrier lifetimes have enabled the use of LT GaAs in FET buffer layers as well as in ultra-fast optical switches. An extension to AlInAs has also been performed and it was seen that variable range hopping is also present in the Asbased ternary.

We report the optical and electronic properties of InP grown at low temperatures in a gas source MBE using dimeric phosphorus produced from cracked phosphine. The conductivity is higher than the equivalent GaAs LT material and does not have the same temperature dependence. The conditions under which growth occurs ie, substrate temperatures, V/ill ratios and annealing is explored. The structural properties, temperature dependence of the conductivity, deep level structure and the photoluminescence properties of the material are also investigated.

The low temperature growth procedure used in the case of GaAs to introduce high concentrations of deep traps such as arsenic antisite defects has been extended to the growth of InP by gas source molecular beam epitaxy. The low temperature growth of InP induces a strong group V stoechiometric deviation (of the order of +1%). On the other hand, Secondary Ion Mass Spectrometry reveals high levels of hydrogen ranging from 3.1018 to 3.1019 cm−3 depending on growth temperature. Undoped layers are found to be resistive without any post annealing. Annealing experiments above 250°C lead to conductive layers suggesting a passivation effect of both shallow donors and acceptors by hydrogen.

Low-temperature (LT) growth of InP by gas-source molecular-beam epitaxy has been studied. Contrary to GaAs, InP grown at low temperature (from 200°C to 410°C) shows ntype, low-resistivity properties. The electron concentration changes dramatically with growth temperature. A model of P antisite defects formed during LT growth was used to explain this experimental result. Ex-situ annealing can increase the resistivity, but only by a factor of about 6. Heavily Be-doped LT InP also shows n-type property. We believe this is the first report of an extremely high concentration of donors formed in LT InP and n-type doping by Be in III–V compounds.