IMEC is focusing its 3D-integration technology developments in 3 distinct directions: 3D-System-in-a-Package (3D-SiP), 3D-Wafer-Level-Packaging (3D-WLP) and 3D-Stacked-IC (3D-SiC). First, the background of these separate approaches will be given. Next the materials and technologies involved, the typical characteristics and the ongoing developments will be discussed. Finally, the roadmap for the 3D-integration in IMEC will be presented.

Currently, 3D integration of semiconductor chips is introduced into high-volume products. While memory and communication will be leading fields of application, automotive will require specific non-standard solutions some of which are in research or development whereas others have already been introduced to production. This paper elaborates on the different opportunities and constraints of automotive applications, presents different technological options and discusses specific solutions considered in research or found in already existing products.

Vertical or 3D integration is taking hold in both the CMOS IC industry and the MEMS industry. The need for smaller devices, lower power, increased functionality, and lower cost are driving the market toward chip and wafer level stacking. Equipment suppliers have been faced with numerous challenges to meet the demands of these emerging bonding applications. This paper will discuss the confederacy of alignment, bonding and materials unions that can lead to successful outcomes in integrated manufacturing.

1. Alignment strategies for 3D integration: IR, BSA, and ISA as they pertain to specific bond methods

2. Pros and Cons of 3D Bonding Techniques (Direct bonds, metal, adhesive, and eutectic)

3. Error analysis in alignment of 3D structures

System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated.

A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented.

Micro-fabrication technology for LSI devices has been progressing technically over time. However, the scenario of continuing to produce ever-finer feature geometries has a low probability. Resolution capabilities will reach a critical limit due to conventional CMOS performance threshold and chip economy. Therefore, to assure continued performance improvements for future devices, front-end fabricators should consider a new 3 dimensional structure (3D-LSI) using a “Through-Si-Via” process. At the same time, the definition of the semiconductor device should be updated to “System & Design Integration (S&DI).” S&DI will provide the needed feedback to launch a new field of clear applications, based on a total system solution with innovative design, fabrication, inspection and evaluation equipment. 3D-LSI and S&DI will have a tremendous impact on the future electronics industries.

The study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Three dimensional (3D) wafer bonding is an emerging technology that may be used to increase transistor densities by stacking devices over devices. The alignment of the wafers and the devices on them is a function of the mechanical capability of the wafer to wafer alignment tool and the thermal conditions of each wafer when bonded. However, as bonded wafers are thinned to 1% or less of their starting thickness the processes of bonding and thinning as well as previous process history affect wafer planarity and silicon stress. The drive to vertically interconnect circuit blocks at the sub-micron scale requires a high density of vertical interconnects and thinning a wafer to less than 5 μm enables through wafer via processing at a scale found in the first layers of the interconnect stack. In this paper the measurement of wafer to wafer alignment was done by comparing a metal pattern on a face down bonded silicon on insulator (SOI) wafer to a complementary metal pattern on the bulk wafer to which it was bonded. The effect of aggressive thinning is evaluated using thinned back to face bonded SOI wafers with functional devices and face down bonded non-patterned SOI wafers thinned after bonding. The face up bonded SOI wafers with functional devices were temporarily bonded face down to a Si-wafer I, thinned to the buried oxide (BOX), face up bonded with benzocyclobutene (BCB) on a Si-wafer II, followed by release of the temporary bond and electrical test. Raman and XRD stress measurements of the non-patterned SOI wafer silicon 70 nm and 110 nm thick SOI Si were taken before and after thinning, and the radius of curvature of the SOI wafers and the bulk wafer substrates was monitored. Thermo-mechanical models of SOI Si stress and bonded wafer curvature are compared to the measured results.

Active Si Interposers (ASI), which are device chips with through Si vias (TSVs) and redistribution wirings, are the focus of this study. A feature of the module is that the redistribution layer includes a stress buffer layer so that stress can be alleviated when it is mounted on a motherboard. For the purpose of this study, it was decided to conduct the process from the backside of the wafer for efficiency of production. One feature of this process is that a device wafer was processed with a glass wafer supported throughout the TSVs' process in order to facilitate process of a thin wafer. However, the maximum temperature of each process was limited. We addressed this problem by the optimization of some of the equipment and the modification of the adhesive that attaches the device wafer to a glass wafer. Finally, a module that was a combination with the ASI and a certain device operated normally. In the last part of this study, the results of the evaluation that studied the impact on the devices of the TSVs' process are presented.