N-channel MOS transistors were fabricated on silicon films that had been recrystallized by an argon ion laser at different power levels. These transistors showed electrical characteristics similar, but somewhat inferior to those devices fabricated on single crystal silicon substrates. These differences are attributed to the presence of trapping states at the grain boundaries of the crystallites in the recrystallized silicon. A coulombic scattering model is presented to explain these differences. In the case of films annealed at low laser power, an additional factor of nonuniform trap state distribution is invoked to explain device characteristics. This model provides an adequate explanation for the observed transport properties of transistors fabricated from recrystallized silicon films.

A review is given of a technique in which compound semiconductor films are produced by direct synthesis from multilayered, polymetallic films deposited onto insulating substrates and laser-irradiated in the CW or pulsed regime. Such films are characterized by a high degree of crystallinity together with optical and transport properties sufficiently close to single crystal ones to allow for various applications in optoelectronics.

GaAs SOI consisting of a sputtered GaAs film on a SiO2 −Si or sapphire substrate is irradiated by CW Ar+ laser beam with a view to investigating its recrystallization. Using AES, x-ray diffraction, TEM and ED, we have studied the compositions, crystal orientations and grain size of the laser-irradiated GaAs films. The possible application of GaAs SOI to devices is discussed on the basis of the experimental results.

InSb thin films on oxidized Si wafers have been recrystallized using a strip heater to generate and scan a narrow molten zone across the film. Grains up to 3 × 10 mm have been produced. Crystallization proceeds in a faceted cellular fashion, the excess solute (Sb) being rejected into subboundaries which often lie along low-index crystallographic directions. A InSb-Sb eutectic structure forms at the subboundaries. The width of the single-crystal InSb between subboundaries is approximately 75 μm. The techniques of planar constriction and subboundary entrainment have been extended to InSb for the selection of single grains and the orelocation of subboundaries. This technology of producing InSb thin films on oxidized Si substrates max, be extendable to other III-V materials, and could lead to novel device structures through the integration of Si and III-V compound devices on the same substrate.

From reported equilibrium partial and total dissociation pressure data for GaAs and melt times derived from reported time resolved reflectivity experiments, estimates have been made of the anticipated rate of As loss. Good agreement was found with experimentally determined As loss. A similar approach using experimentally determined Ga loss data allowed estimates of the maximum temperatures reached during pulsed laser annealing. These temperatures are considerably higher than suggested in thermal modelling studies. The boiling point of Ga gould be exceeded at incident laser energies >0.8 J cm−2.

We have studied the effects of pulsed laser irradiation on silicon implanted, thermally activated , Calcia Stabilized Zirconia (CSZ) capped GaAs substrates. Reference substrates have also been irradiated in air for comparison. CSZ as a solid electrolyte has been used to chemically reduce the GaAs surface native oxides prior to irradiation while maintaining the surface stoechiometry. Our results indicate a spectacular decrease in defect density after laser irradiation of the CSZ capped-native oxide free samples, as compared to the samples irradiated in air.

Pulsed laser annealing has been made for Te or Znimplanted GaP and Si-implanted GaAs in argon gas atmospheres in a pressure range of 1 to 1000 bar. Optical absorption measurement indicates that pulse annealing under pressures higher than 300 bar forms surface layers with a high crystallinity without appreciable evaporation of P or As. This pressure effect is discussed from the viewpoint of diffusion length of evaporated atoms during the annealing time.

Rapid thermal process utilizing radiation from halogen lamps has been used to post-anneal ion-implanted GaAs. Annealing conditions for Si implants in GaAs are discussed from the view point of applying this technique to GaAs MESFET fabrication. Also, the properties of S and Mg implants in GaAs followed by rapid thermal annealing are comparatively studied with the results after conventional furnace annealing. High electrical activation and minimized implant diffusion for both low and high dose implants are the principal features of this technique. The fabricated MESFET showed much higher transconductance without any anomalous characteristics, indicating this technique to be a promising alternative to conventional furnace annealing.

High dose antimony and tellurium implanted (100) GaAs wafers have been annealed in the solid phase under various time/temperature conditions using a conventional furnace, a rapid incoherent light source and a continuous wave CW Argon ion laser. The samples were capped with RF sputtered SiO2 prior to annealing and analysed using 2MeV He++ ion channeling to determine the solid solubility of the implanted ions. Results indicate that the Te is more soluble than Sb; highest solubilities measured were 6 × 1020cm−3 for Te and 1.3 × 1020cm−3 for Sb.

Heatpulse rapid thermal annealing was used to activate Si implants of 3.5 × 1012cm−2 at 100 keV and 1.0 × 1013 and 1.0 × 1014cm−2 at 200 keV into semi-insulating GaAs. The effects of Si3N4 encapsulation, anneal temperature and time, and substrate Cr-doping level were investigated. The annealed samples were characterized with C-V, Van der Pauw, differential Hall, and SIMS measurements. Conventional furnace anneals were carried out for comparison, and in all cases, Heatpulse anneals produced sharper carrier concentration profiles. 84% electrical activation was obtained for the 200 keV, 1.0 × 1013 cm−2 implant after a 950°C, 5 sec. Heatpulse anneal. Capped Heatpulse anneals produced less Cr depletion from the implanted region than furnace anneals.

Halogen lamps are used to anneal implanted GaAs. Surface protection is obtained by mouting the substrate in a sandwiched configuration between a silicon and a quartz plate. Raman scattering measurements are carried out to follow simultaneously lattice reconstruction and surface degradation due to Arsenic loss. The evolution of the Raman spectra is compared to a T.E.M. analysis carried out on the same samples.

The electrical properties of IR radiation transient annealed Si implanted semi-insulating GaAs are presented for 100 keV ion doses from 3 × 1012 to 3 × 1014 cm−2. For wafers implanted with 3 × 1012 cm−2 doses, suitable for FET channel layers, carrier concentration and drift mobility profiles were determined from C-V and transconductance measurements on fat FET structures. Optimum electrical activation and carrier concentration profiles were obtained for peak pulse temperatures of 930–950°C. Van der Pauw measurements were made on substrates implanted with Si doses ≥ 1 × 1013 cm−2 to determine sheet carrier concentration and Hall mobility. The peak pulse temperature required to give optimum activation efficiency is found to increase with dose. The results presented here demonstrate that undoped substrates are preferable to Cr-doped substrates for low dose device applications.

This paper discusses the properties of high intensity lamp-annealed silicon or beryllium-implanted GaAs and InP samples. We find this annealing process can result in efficient activation of dopants. Conventional furnace annealing at the same temperature does not result in increased electrical activation of the dopants. High fluence silicon implants can be activated in anneal times as short as 2 seconds, while low fluence silicon implants require more extended annealing. Activation of low fluence implants in GaAs depends strongly on the properties of the bulk semiinsulating material.

A parametric study is presented of CVD and RF sputter deposited SiO2 and PSG dielectric caps for incoherent lamp annealing of InP. Both deposition and annealing parameters are studied. We observe that CVD caps provide reliable mechanical protection during lamp annealing up to maximum bulk temperatures of 830°C, while sputtered deposited SiO2 caps perform well ,up to 850°C. We find however that sputter deposited caps introduce process related conduction into both unimplanted and implanted semi-insulating InP. Electrical activation of implanted dopants is also studied as a function of capping technioue. Lamp annealing of InP protected by caps with CVD phosphorus doped SiO2 in contact with the InP surface, results in excellent activation efficiencies in Si+ implanted material. When properly capped and annealed, we observe electrical profiles whose shape more nearly approaches theoretical LSS, than those previously reported.

PEBA induced thermal effects in GaAs and InP have been simulated. Monte-Carlo calculation has been used to determine universal electron energy loss functions in the 5–50 keV energy range for these materials. Similar electron depth-dose profiles of a polykinetic electron beam pulse is deduced in both GaAs and lnP. A simple adiabatic approach is sufficient to establish relationship between melting depths and fluences. Thermal effects homogeneity and surface degradation are discussed for both crystalline and amorphous materials using variable electron energy deposition profiles. Correlation is made between experimentally measured degradation thresholds and calculated fluence windows within which melting effects are expected.

Raman scattering and luminescence spectroscopic techniques were applied to the study of ion implantation of InP and its annealing by a lamp, oven, or laser beam. It was found that both characterization techniques give important information on surface layer transformation during implantation and annealing.

The lattice reconstruction produced by a pulsed laser irradiation in heavily damaged GaAs layers is studied. Spatially resolved Raman measurements are used to characterize the crystalline quality after the annealing cycle produced by a O-switched Ruby laser or by a picosecond pulsed Nd-YAG laser. The continuous evolution in the Raman spectra is usèd to follow the crystal recovery as a function of the irradiation parameters.

Epitaxial Ni and Co silicides have been fabricated using pulsed laser melting. Interfacial instabilities and cell formation are suppressed during the liquid-phase epitaxy by melting mono or disilicide layers. Single crystal NiSi2 and CoSi2 films have been grown on (100) and (111) Si following a post-anneal. This method does not require UHV deposition or reaction techniques.

Short duration, incoherent light from a xenon lamp has been used to grow nickel silicides on silicon single crystals from evaporated nickel films. The formation of these silicides was studied by Rutherford Backscattering Spectrometry, channeling, sheet resistivity, and transmission electron microscopy as function of induced temperature (550– 775°C), exposure time (8– 25 sec), and silicon orientation (>111<, >110<, and >100<). Epitaxial NiSi2 films were formed for temperatures above ˜675°C whereas polycrystalline NiSi films were formed below this temperature.

The formation of composite TaSi2/n+ Poly-Si silicide films through the use of rapid thermal annealing (RTA) is investigated by x-ray diffraction, four point probe, scanning Auger microprobes (SAM) with ion sputter etching, transmission electron microscopy (TEM), scanning electron microscopy (SEM), and capacitance-voltage (C-V) measurements. 0.2 μm polysilicon is deposited on oxidized Si wafer by LPCVD and doped with phosphorus. A layer of 2200 A TaSix is then co-sputtered on polysilicon samples from separate targets. These as-deposited films are then annealed by RTA in an argon ambient for 1 sec. and 10 sec. at various temperatures. X-ray diffraction and SAM results show the rapid formation of a uniform stoichiometric tantalum disilicide via Si migration from polysilicon. TEM micrographs show simlilar results for samples annealed at 1000°C in furnace for 30 min. or by RTA for 1 sec., exhibiting average grain size greater than 1000 A. Sheet resistance of samples annealed by furnace annealing and RTA are comparable. SEM micrographs indicate that the surface morphology of the RTA-annealed sample is superior to that obtained by furnace annealing. These results show that RTA may offer a practical solution to low-resistivity silicide formation in VLSI circuits.