The present understanding of the properties of thin (≤0.6 μm) heteroepitaxial Si films grown on single-crystal bulk and thin film insulators is reviewed. Three areas are covered: (a) as-deposited Si films on bulk insulators, with particular emphasis on sapphire and cubic zirconia (b) post-growth processing methods to reduce the defect concentration and compressive strain in such Si films and (c) the growth and properties of monocrystalline insulating films on bulk Si and of Si on such films. The desired characteristics of the insulating material are given, and it is shown that the mismatch in thermal expansion coefficients between the insulator and Si dominates the properties of heteroepitaxial Si films. Present and future areas of application for Si-on-insulator technologies are briefly described, and directions for further studies are proposed.

CMOS is considered as a prospective technology in the VLSI era because of its low power consumption and high driving capability. While ordinary bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area, operation speed and latch-up problem due to the need for isolation wells. SOS is an inherent good partner of the CMOS circuits owing to the simple and perfect isolation. SOS technology, however, has the problem of high wafer cost. Consequently, SOS technology is best applied to high performance logic devices. Latest results of 8k-gate CMOS/SOS gate array and 16×16bit multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time, respectively, which compete with ECL devices. Application of SOS devices down to 1μm is also promising for very high speed operation. A 78ps gate delay is achieved by double solid phase epitaxy and 1μm technology. INTRO

Complementary Metal-Oxide-Semiconductor (CMOS) devices and circuits with minimum feature sizes of about 1 μm were fabricated in 0.5-μm-thick epitaxial Silicon-On-Sapphire (SOS) films. The films were modified by ion implantation and subsequent solid phase recrystallization processes which reduced the total microtwin concentrations in the Si layers by more than a hundredfold, while increasing electron and hole channel mobilities between 40 to 50%. Leakage currents were reduced by over 2 orders of magnitude, while drive currents and subthreshold slopes showed significant improvements over as–grown SOS films. Propagation delays of less than 80 psec were obtained for CMOS/SOS inverters with Leff = 0.6 μm.

Silicon on insulator structures consisting of a buried dielectric, formed by the implantation of high doses of oxygen ions, have been shown to be suitable substrates for LSI circuits. The substrates are compatible with present silicon processing technologies and are confidently expected to be suitable for VLSI circuits. In this paper the microstructure and physical properties of this SOI material will be described and the dependence of these characteristics upon the implantation conditions and subsequent thermal processing will be discussed. With this information, it is then possible to outline the specification for a high current oxygen implanter.

Porous silicon is formed by the anodic dissolution of p-type silicon in aqueous hydrofluoric acid. Because of its very high porosity, this material can be rapidly cKidized to form thick (˜10 μn) oxide layers with minimal stress on the underlying silicon wafer. A remarkable property of porous silicon is that preserves the crystalline orientation of the substrate despite removal of more than half of the silicon in the etched region, providing a suitable surface for the growth of epitaxial layers. Several schemes for dielectric isolation have been suggested which take advantage of these unique properties. In this paper, the mechanism of porous silicon formation will be presented and the relative advantages and disadvantages for practical device applications will be discussed.

The fabrication of silicon-on-insulator structures was examined utilizing epitaxial growth of Si films on porous silicon and subsequent enhanced oxidation of the porous substrate. Porous silicon films have been formed by local anodic dissolution of silicon wafers in HF, while retaining the single crystalline structure. Low temperature liquid phase epitaxy (LPE) from saturated Ga solutions as well as molecular beam epitaxy (MBE) and laser induced epitaxy have been studied. Transmission electron microscopy (TEM) has demonstrated that all three techniques can achieve crystalline Si film growth on porous silicon. Surface smoothness and crystal perfection of the resulting epitaxial layers varies considerably with each technique.

Energy sources used to convert polycrystalline silicon-on-insulator films to single crystal through melting and recrystallization have included electron beams, lasers, graphite strip heaters, and incoherent light from tungsten halogen and vapor arc lamps. This review focuses on incoherent light recrystallization of polycrystalline silicon; comparing tungsten filament and vapor arc lamp sources, and linear zone melting vs. uniform illumination. The discussion includes material redistribution, defect formation, and the dynamics of melting.

Two scanning methods for laterally-seeded recrystallization of striped silicon-on-insulator/seed structures with an elliptical laser beam are discussed. One method requires repeated remelting of the silicon film and is controlled by the temperature of the substrate, which is locally heated by the beam. This method results in very few defects and single-crystal silicon-on-insulator stripes up to 50 μm wide. The second method involves little remelting and is primarily controlled by the lateral offset of the beam with respect to the stripes. Single-crystal silicon-on-insulator stripes up to 40 μm wide have been obtained, with defects consisting primarily of stacking faults and twins, as well as some grain boundaries. These defects show little effect on MOS transistor leakage current.

Semi-insulating polycrystalline silicon films have been used as matching layers in micro-zone-melting recrystallization experiments of silicon-on-insulator (SOI) structures. The effect of the laser irradiation on the structural composition and crystallographic properties has been investigated by transmission electron microscopy and Auger electron spectroscopy. CO2 laser processing has been shown to lead to redistribution of oxygen and interface segregation of thin oxide and silicon zones.

Line-shaped laser and electron beams in combination with halogen-lamp substrate heating were used to fabricate single-crystal SOI films. Electron-beam and laser systems were developed to achieve a minimum beam cross section of 10–100 microns and aspect ratios up to 70. Unseeded SOI films were fabricated with a (100) textured single-crystal structure. Seeded films were recrystallized with 20 × 80-micron single crystal islands with no low-angle grain boundaries. A process window of 1 to 10 percent in electron-beam power was measured. Single-crystal films were obtained at a line-scan velocity up to 2 cm/s suggesting a potential throughput of about 100 wafers per hour. The high scan velocity allows for minimizing the high-temperature cycle to under 30 seconds that the wafer is exposed to during recrystallization. This short temperture cycle is compatible with the fabrication of three dimensional devices, since unwanted diffusion and substrate damage are minimized.

Residual electronic deep levels in fully – processed, cw laser – crystallized silicon thin films on fused silica were measured by transient capacitance spectroscopy, supplemented with capacitance – voltage techniques. The test devices were metal – oxide – silicon thin – film capacitors with p – type conductivity. The hole emission spectra are dominated by a continuous distribution of deep levels in the lower half of the silicon band gap which are associated with the Si – SiO2 interface; the spectra also display the effects of surface generation. The interface – state density near midgap is estimated to be 6×1010 eV−1 cm−2, and there are no detectable bulk deep levels with densities > 1×1014 cm−3.

Recrystallized SOI structures offer possibilities for new classes of devices, as well as improved performance of more conventional circuitry. Single-layer and multilayer circuits are possible. For large–geometry devices unseeded films should be satisfactory, but seeding will be required for high–performance, small–geometry circuits. In addition to the quality of the recrystallized film and the substrate, the properties of the interfaces must be optimized. The characteristics of each potential heat source must be considered when selecting one for a specific SOI structure; different sources will be optimum for different applications. The evolution of SOI device structures can be seen by considering different realizations of CMOS cells. SOI structures can be applied to conventional circuits and also should allow efficient integration of entire systems with closely interacting functions.

High-speed NMOS depletion-load ring oscillators and dynamic shift registers have been fabricated from laser-crystallized silicon thin-film transistors (TFT's) on fused quartz. We report on optimization of circuit fabrication process involving ion implantation and high temperature cycles to achieve inverter gains, logic thresholds, and input noise margins appropriate for logic operation. Characteristics of discrete devices are also used to evaluate a process simulator and a device simulator as tools for future designs.

We have developed a procedure to optimize electron mobility and leakage currents in MOSFETs fabricated in laser recrystallized polysilicon films on SiO2. A shaped laser beam was used to obtain grain boundaries aligned with the current flow in MOS transistors. To suppress grain boundary diffusion, rapid thermal annealing replaced all high temperature processing steps subsequent to source and drain implantation. By combining these two approaches, functional transistors as short as 1.5 μm were obtained, and also 2 μm-channel 19-stage ring oscillators with 115 psec/stage propagation delay.

An offset-gate structure was used to fabricate p-channel MOS transistors in laser-recrystallized silicon-on-insulator (SOI) films. The breakdown voltage increased from about -18 V with a conventional gate structure to about -38 V with the offset gate and was then limited by bulk breakdown in the film, rather than by the high fields near the gate drain overlap region. Simulations indicate that breakdown voltages of about -60 V can be achieved in the structure used, provided that the back-surface fixed-charge density is limited to 1×10″ cm−2.

Spreading resistance has been measured for various types of grain boundaries formed on graphite heater recrystallized SOI samples (G-SOI) or laser strip beam-recrystallized SOI samples (L-SOI) in order to identify the characteristic relation between the morphological/structural variation of the boundary defects and their electrical transport properties. In general, the resistance values across L-SOI sub-boundaries are higher than those across G-SOI sub-boundaries. TEM analyses reveal evidences of higher degree of crystallographic mismatch (up to 10°) in L-SOI sub-boundaries than that (1 – 2°) in G-SOI sub-boundaries. The measurement also revealed the evidences of counter-doping near the seed areas where the epitaxial growth initiated.

Nearly two decades of work in fabricating active devices in small grain LPCVD polysilicon by various workers has shown that the material is generally suitable for junction diodes and MOSFETs [1–10]. Recently, there has been a considerable activity in the domain of beam recrystallization of polysilicon. One of the goals of this effort is 3-D integration for VLSI. These recrystallization techniques require several years of industrywide effort before they become acceptable tools in IC manufacturing. However, there exists a great demand today, especially in large memories, for an SOI MOSFET that can be integrated in existing bulk silicon based technologies.

Fortunately, acceptable MOSFETs can be manufactured in small grain poly-silicon without resorting to beam recrystallization [11–13]. One consistent problem with small grain polysilicon MOSFETs has been a high threshold voltage, which makes these devices unacceptable for standard IC applications that require 5V operation. It has been shown that this characteristic can be remedied by proper device design [11–13]. In particular, thin gate insulator, accumulation mode behaviour, and some form of grain boundary passivation, used alone or in a combination, are effective means of reducing threshold voltage.

The other problem of the polysilicon devices has been high leakage current. This is a result of defects in polysilicon. It has been shown that grain boundary hydrogenation drastically reduces the leakage current by passivating these defects [11–13]. As a result, it is possible to manufacture MOSFETs, in small grain LPCVD polysilicon, with on to off current ratio of seven orders of magnitude.

With improved device design, it has been possible to build short channel p-channel and n-channel MOSFETs with arbitrary threshold voltage and leakage current of the order of 1 pA/μm channel width. The channel mobility is about 10 cm2/V sec. The on to off current ratio is about seven orders of magnitude. Despite the low mobility, these devices are useful for a variety of high density memory applications.

Since no nonstandard materials, tools and processes are required in the fabrication of these devices, manufacturable 3-D integration processes are presently possible with such devices. Besides permitting useful products today, this strategy allows construction of a design and manu-facturing infrastructure that will facilitate infusion of future 3-D concepts in bulk silicon technologies.

We have used p-channel devices built in small grain LPCVD polysilicon to develop a 2 μm stacked CMOS process. We have fabricated 64K static RAMs with this process. The cell size is 307 sq.μm and chip size is 55000 sq. mils. The access time is 120 ns. This provides a demonstration of our strategy.

Seeded lateral epitaxial laser-recrystallization of silicon film on SiO2 is applied to fabricate 3-dimensional (3-D) integrations: 3-D CMOS 7-stage ring oscillators. Top p-channel Si-gate SOI MOSFET's are fabricated in the seeded recrystallized silicon directly above bottom n-channel Si-gate bulk MOSFET's with insulator in between. The recrystallized silicon at the seed region can be utilized for buried contact to interconnect bottom and top MOSFET's. At the arsenic implantation step to fabricate source and drain of the bottom MOSFET's, ions are not implanted into the seed region to prevent heavy doping and crystal disorder there; otherwise the dopant diffuses laterally and residual crystal disorder disturbs the epitaxial recrystallization. After the laser-recrystallization, the seed region is implanted with phosphorus to interconnect the top and bottom MOSFET's.

The Ar+ laser irradiation is performed with a 10 W power, a 50 μm spot size, a 13 cm/s scanning speed and a 13 μm step at 400 °C in air. Propagation delay of 460 psec is obtained for the seven stage 3-D CMOS ring oscillator at a power supply voltage of 17 V for a channel length of 3 μm and a channel width of 18 μm. In the seeded SOI films, grain boundary generation and crystal orientation can be controlled.

A seven mask CMOS process that provides vertically integrated structures with joint gates is described. The structures have been characterized as individual NMOS and PMOS transistors. An implant technique will be described which may permit the fabrication of fully self-aligned CMOS structures.

We report the fabrication of mutually self-aligned IGFET's in two silicon layers which are separated by a thin dielectric film. The transistors are configured such that the heavily doped source and drain regions of a transistor in one layer also serve as the gate electrodes for transistors in the other layer. One application of this three-dimensional technology is the implementation of a compact four-transistor “staggered” CMOS latch circuit which can be used to form part of a static random-access memory cell.