Fundamental understanding of the silicon stresses and their changes with traditional wire-bonded and flip chip packages is critical to address the performance and reliability improvements in new technologies. Recently we have developed a novel technique for non-destructive measurements of complete strain state (and thereby the stress state) of the single crystal (bulk Si) by tracing the relative change in direction of an x-ray beam diffracted from a stressed crystal. This is based on the relationship between the stress state in a crystal and the local lattice plane orientation. Experimentally, this can be achieved by using a large area synchrotron white beam in conjunction with a precision grid of x-ray absorbing material placed in the path of the beam. The grid breaks the X-ray beam into an array of micro-beams that are diffracted by the single crystal sample to produce an integrated x-ray topograph on which the inverse grid image is distorted due to changes in the paths of diffracted microbeams i.e. an x-ray reticulograph is created. The distortions are a result of the variations in the diffracting lattice plane orientation produced by strain present in the crystal. By measuring this distortion on multiple topographs through the electronic package and applying the ray tracing principle, the entire strain state of the silicon can be calculated and mapped for the entire sample. We have carried out stress mapping of the silicon device in the package by applying this non-destructive and non-invasive technique.

Heat dissipation in electronics packaging can be highly dependent on Thermal Interface Materials (TIM). TIM contact, compliance, and conductivity can be the dominant limiting factors in the overall conduction heat transfer across the interface. Mixing multiwall Carbon Nanotubes (CNTs), which have high thermal conductivity, with other thermally conducting materials holds great promise as TIM fillers and has been shown to have higher thermal performance than commercial TIM ‘1’. Such mixtures possess greater thermal conductivity as a result of increased thermal conduction paths through highly conductive, high aspect ratio CNTs.

In this work, we develop and test an advanced apparatus based on the ASTM D5470-06 standard to measure thermal interface resistance. Our experimental findings quantify the thermal performance trends of industry-standard TIM Arctic Silver® 5 along with hybrid TIM mixtures of Arctic Silver®5 and varying weight ratios of CNTs. Early experimental findings show that Arctic Silver®5 mixed with 0.5 to 1% multiwall CNT by weight may improve thermal conductivity over pure Arctic Silver®5.The goal of this research is to investigate the viability of integrating CNTs with commercial products as improved TIM for electronic cooling in chip packages.

A solder ball is the key material of the bump fabrication in the BGA and μBGA high integrated packaging. The nodulizer type is the main factor to affect the quality of the solder ball. In the paper the solder balls are fabricated by the fine wire cutting–remelting method. The influence of different nodulizers on the real sphericity and the surface appearance of the solder balls are investigated. Results show that, the real sphericity of the 63Sn37Pb solder balls is maximum and the surface quality of the solder balls is the best compared with the engine oil, heavy oil and silicon oil when the arachis oil is used as the nodulizer.

Vertically aligned carbon nanotubes (VACNTs) grown on bulk copper substrate are of great importance for CNT real-life applications as thermal interface materials in microelectronic packaging. However, their reproducible synthesis has been a great challenge so far. In this study, by introducing a well-controlled conformal Al2O3 support layer on the bulk copper substrate by atomic layer deposition (ALD) prior to the deposition of the iron catalyst layer, we reproducibly synthesize VACNTs of good alignment and high quality on the copper substrate, using a conventional thermal chemical vapor deposition process. The alignment and the quality are characterized by scanning electronic microscopy and Raman spectroscopy, respectively. The roles of the conformal Al2O3 support layer are discussed. A kinetics-controlled growth mechanism is shown. This progress provides a viable VACNT commercial application for thermal management, on the basis of which, we show a recent progress on a state-of-art Si/VACNT/Cu assembling process, named “chemical anchoring”. The high quality of the VACNTs on the copper growth substrate and the covalent bonding formed between the VACNTs and the silicon mating substrate greatly reduces the thermal resistance of the VACNT-mediated thermal interface.

A three dimensional thermal-fluid and stress model of a single chip SiC power sub-module was generated using ANSYS in order to determine the maximum temperature and deformation under various conditions. The effects of heat flux, working fluid temperature and differential pressure on temperature and thermal stress contours were of particular concern. Steady state analysis with water as the working fluid, a simulated heat flux of 11.12×104 W/m2, an interface coupling film coefficient of either 30 or 200 W/m2-K between the cooling plate and fluid, and ambient film coefficients from 6 W/m2-K to 300 W/m2-K, predicts maximum device junction temperatures between 374 and 316 K, and corresponding deformations from .0351% to .0293%. Under the same boundary and loading conditions, but with air as the working fluid, the deformations reached .0405% to .0296%, with temperatures between 427 and 316 K. Transient analysis also showed junction temperatures in the predicted range and determined the time to reach steady state to be between 150 and 2500 seconds depending on the boundary conditions. Experiments were conducted in order to validate ANSYS results.

Viscoelastic stress relaxation occurs at operating temperature in underfill materials of flip-chip packages with high power devices. Multi-level finite element analysis is performed to study the impact of the viscoelastic relaxation on package reliability. The stress simulations reveal that the relaxation in underfill material leads to higher stress concentration in solder bumps. The failure analysis shows that the induced high stress develops higher crack driving forces. The results demonstrate that the underfill material property such as viscosity can shift failure mode from die corner delamination to near bump delamination. Therefore, the numerical study can be used as a guideline to select underfill material for package reliability improvements.

Low dielectric constant (low-k) materials are currently being incorporated into advanced microelectronic devices to improve or maintain performance. As the dielectric constant is reduced, so are its mechanical properties. These reduced properties have recently been related to chip-package interaction (CPI) failures. Significant effort has focused on eliminating CPI failures through engineering of copper crackstop structures. However, published data suggests that crackstop engineering needs to occur at each technology node to ensure CPI reliability. In this study, the focus is on repairing interfacial delaminations with chemistry specific coupling agents rather than attempting to stop them with a specially designed crackstop structure. Critical adhesion values and corrosion resistance of the repaired interfaces are compared to the original interface. The application of the repair chemistry in an integrated structure is discussed along with the potential impact on reliability.

As electronic systems are scaling down further and further, there is the constant need to utilize all the board area with maximum efficiency. Since passive components occupy most of the space on boards, it is very important to scale them down. New techniques allow for “integrated” passives as opposed to their discrete counterparts. Integrated capacitors can be embedded within the substrate, leaving room for other components on the board surface. In order to improve the area efficiency of these integrated capacitors, researchers have formed multilayered capacitors in the past. This increases the capacitance density, but is time consuming and expensive due to too many process steps. With increased circuit density, a currently demonstrated dielectric, Ta2O5, could be replaced with a potential high-k dielectric that can store more charge in a smaller area than a capacitor with Ta2O5. Niobium pentoxide (Nb2O5) with k∼41 is an emerging dielectric for high-k capacitor applications. This paper investigates niobium pentoxide as a next generation high-k planar capacitor dielectric. Niobium pentoxide dielectric was formed by reactive sputtering and anodization. Dielectric characterization was done using X-ray photoelectron spectroscopy (XPS), Transmission Electron Microscopy (TEM), and Atomic Force Microscopy (AFM). Thin film planar capacitor structures were fabricated using Nb2O5 dielectric and electrically characterized. The results presented include dielectric material characterization, design, capacitance, and breakdown voltage measurements.

This study examines the effect of cyclic damage on the constitutive response and microstructural evolution of SAC305 solder. Cyclic damage is induced through isothermal, mechanical cycling tests at high strain rate and room temperature, using modified lap shear microscale specimens (180μm wide solder joint). The properties of interest are elastic, plastic, yield, and viscoplastic material constitutive behavior. In the current study, creep strain accumulation is accommodated when determining the constants, unlike those reported in prior studies [1]. Insights into the evolution of the measured properties are provided by correlating previously reported microstructural grain evolution of microscale SAC305 solder as a function of cyclic damage [2, 3].

The hysteresis response and the elastic, plastic and yield measurements from the initial cycles show significant piece-to-piece variability (similar to prior virgin state viscoplastic measurements [3]). The scatter arises since as-reflowed SAC solder joints at length scales of 200μm consist of only a few anisotropic Sn grains that make the joint mechanically inhomogeneous. However, when subject to mechanical cycling fatigue at room temperature these joints undergo grain homogenization due to recrystallization, which is a possible explanation to the drop in scatter with progressing damage. The observed grain evolution is similar to that seen in solder joints under life-cycle loading.

The elastic-plastic response and yield strength of SAC305 solder do not show significant contribution from creep deformations at the chosen load levels. The properties degrade with increasing accumulated cyclic damage, at a rate that is proportional to the severity of the cyclic load. The yield stress measurements suggest that SAC305 obeys an independent hardening rule, rather than isotropic or kinematic hardening. The performance of a continuum damage mechanics based model from prior studies in representing the measured degradation in elastic, plastic and yield properties is discussed [4,5].

Comparison of the creep behavior of cycled SAC305 specimens (at 50% load drop) with that of uncycled specimens shows that the effective creep compliance and effective secondary creep strain rate increase significantly. As a point of comparison, the creep resistance of cycled SAC305 specimens is even lower than that of as-reflowed Sn37Pb specimens. Similar changes are seen in the stress relaxation behavior. Challenges and limitations of the current studies are included.

Manufacturers of modern high performance military and commercial electronics are steadily increasing the power density of the components of their devices. The increase of small component size and/or higher power densities results in large component heat flux levels. In applications from laser diodes, radar transmit/receive (T/R) modules and LED lighting, solutions to thermal issues through advancements in heat spreaders and heat sink design are needed to continue the performance improvement of these devices and structures.

Advanced materials for heat spreaders should have high thermal conductivity, a coefficient of thermal expansion (CTE) that matches the electronics die, and a reasonable cost. Diamond, for example, has the highest thermal conductivity of any known solid material at room temperature, combined with a high modulus of elasticity, but has a CTE mismatch with silicon (die material) and a high relative cost.

As an alternative material, PYROID® HT pyrolytic graphite has a thermal conductivity of 1700 W/m °K in the x-y plane of the material (7 W/m °K in the z plane), costs more than 250 times less than diamond produced by chemical vapor deposition (CVD), and has a modulus of elasticity much lower than diamond. The lower modulus of elasticity of this material results in an order of magnitude lower thermal stress level between the spreader and the die than diamond.

In one case study involving a laser diode cooling application, the spreader/die is nearly two-dimensional. Thus, pyrolytic graphite can be oriented with high conductivity in the direction into the spreader and away from the die (x-y plane), and the low conductivity direction (z direction) along the die where minimal conduction is needed. For the cases where a three-dimensional spreader is required, laminated composite structures of pyrolytic graphite have been developed where the equivalent isotropic conductivity is over two times greater than the conductivity of copper. The graphite layers are metallized so that they can be bonded together by soldering and/or dies can also be attached by soldering. The adhesion of the metal layers to the graphite has been tested with several standard techniques. Graphite metallization techniques, thermal performance modeling and analysis of stress levels due to CTE mismatching will be discussed in this paper.

Creation of superhydrophobic self-cleaning surfaces is an important objective for a variety of applications. Indeed, numerous routes to generate superhydrophobic surfaces have been proposed. In this paper, a facile way of forming superhydrophobic surfaces is reported that uses Au assisted HF/H2O2 etching of silicon wafers. The Au layer was deposited onto a silicon wafer via e-beam evaporation. By controlling the evaporation and etching times, the surface roughness can be manipulated and superhydrophobic surfaces with reduced light reflection can be generated. Contact angles were measured with a CCD camera equipped goniometer; these values determined the water repellency. Light reflection on the as prepared black surfaces was measured to assess the efficiency for low cost solar cell applications. This approach offers a new way both to theoretically study the surface roughness effect and to investigate engineering applications of self-cleaning surfaces in solar cells, MEMS, anti-bacteria coating, and microfluidic devices.