The focus of this issue of MRS Bulletin is to explore the impact of materials science and technology on microelectronics packaging and integration. Progress in microelectronics packaging has been intimately tied to the continuous advances made in the associated materials, process technologies, and design tools. This is especially true now, as packaging moves into an era driven by the need for complex system-level solutions. This issue is our attempt to present the current status of microelectronics packaging technology and integration and to highlight various perspectives on the future evolution of the field.

Historically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.

Advanced three-dimensional (3D) packaging techniques for electronic components are promising for the realization of “systems-in-packages.” Three-dimensional packages require the use of a variety of materials within a small physical size range. Materials selection is therefore critical from electrical, optical, mechanical, structural, thermal, and manufacturability viewpoints. The materials combination depends also on the intended application for the 3D packaged modules. This article reviews 3D packaging approaches, materials classes, and examples. Three-dimensional packaged systems using judiciously selected materials offer performance advantages that cannot be provided by planar implementation.

Packaging of solid-state power electronics is a highly interdisciplinary process requiring knowledge of electronics, heat transfer, mechanics, and materials science. Consequently, there are numerous opportunities for innovations at the interfaces of these complementary fields. This article offers a perspective of the current state of the art and identifies six specific areas for materials-based research in power electronics packaging. The emphasis is on identifying the underlying physical relationships that link the performance of the power electronics system to the microstructure and architectural arrangement of the constituents.

Microelectromechanical systems (MEMS) devices can be delicate structures sensitive to damage from handling or environmental influences. Their functionality may furthermore depend on sealing out the environment or being in direct contact with it. Stress, thermal load, and contaminants may change their characteristics. Here, packaging technology is challenged to extend from microelectronics toward MEMS and optoelectronic MEMS (MOEMS). Today's approaches rely on modified single-chip packages derived from the microelectronics industry, wafer-level capping to enable the device to be packaged like an integrated circuit, or highly specialized packages designed to complement the function of the MEMS device itself. Selecting the proper packaging method may tip the scale toward a product success or a product failure. Choosing the right technology, therefore, is a crucial part of the product design.

Vacuum packaging of high-performance surface-micromachined uncooled microbolometer detectors and focal-plane arrays (FPAs) for infrared imaging and nonimaging applications, inertial MEMS (microelectromechanical systems) accelerometers and gyroscopes, and rf MEMS resonators is a key issue in the technology development path to low-cost, high-volume MEMS production. In this article, two approaches to vacuum packaging for MEMS will be discussed. The first is component-level vacuum packaging, a die-level approach that involves packaging individual die in a ceramic package using either a silicon or germanium lid. The second approach is wafer-level vacuum packaging, in which the vacuum-packaging process is carried out at the wafer level prior to dicing the wafer into individual die. We focus the discussion of MEMS vacuum packaging on surface-micromachined uncooled amorphous silicon infrared microbolometer detectors and FPAs for which both component-level and wafer-level vacuum packaging have found widespread application and system insertion. We first discuss the requirement for vacuum packaging of uncooled a-Si microbolometers and FPAs. Second, we discuss the details of the component-level and wafer-level vacuum-packaging approaches. Finally, we discuss the system insertion of wafer-level vacuum packaging into the Raytheon 2000AS uncooled infrared imaging camera product line that employs a wafer-level-packaged 160 × 120 pixel a-Si infrared FPA.

The drive toward higher density and higher performance in integrated circuits creates a need to keep interconnects short and eliminate layers of packaging. In this article, we propose a novel, ultrahigh-density (exceeding 104 leads per cm2), compliant, wafer-level, input/output interconnection technology called “sea of leads” as a key enabling technology for future high-performance microsystems. The mechanical compliance is addressed through slippery leads (leads released from the surface) and embedded air gaps. The ability to fabricate embedded air gaps has enabled the integration of optical interconnects with high index-of-refraction mismatches between the core and cladding.

The trend for microelectronic devices has historically been, and will continue to be, toward a smaller feature size, faster speeds, more complexity, higher power, and lower cost. The driving force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunications, rf applications are beginning to drive many areas of microelectronics that traditionally were led by developments in microprocessors. An increasingly dominant factor in rf microelectronics is electronic packaging, and the materials needed to create the package, because the package materials strongly affect the performance of the electronics. Many challenges remain for the packaging of microprocessors as well. These challenges include increased speed, the number of input/output interconnects, decreased pitch, and decreased cost. This article highlights the key issues facing the packaging of high-performance digital and rf electronics.