Hostname: page-component-586b7cd67f-t7czq Total loading time: 0 Render date: 2024-11-22T20:35:57.272Z Has data issue: false hasContentIssue false

Critical Aspects of High-Performance Microprocessor Packaging

Published online by Cambridge University Press:  31 January 2011

Get access

Abstract

Historically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1.Mahajan, R., Brown, K., and Atluri, V., Intel. Technol. J. Q3 (August 22, 2000), available from http://developer.intel.com/technology/itj/q32000.htm (accessed October 2002).Google Scholar
2.Mencinger, N.P., Intel. Technol. J. Q3 (August 22, 2000), available from http://developer.intel.com/technology/itj/q32000.htm (accessed October 2002).Google Scholar
3.Moore, G.E., Electronics 38 (8) (1965) p. 114.Google Scholar
4.Mahajan, R., Nair, R., Wakharkar, V., Swan, J., Tang, J., and Vandentop, G., Intel. Technol. J. 6 (2) (2002), available from http://developer.intel.com/technology/itj/2002/volume06issue02/index.htm (accessed October 2002).Google Scholar
5.Choksi, G., Intel University Course on Packaging (Intel Corp. Internal Document, January 2002).Google Scholar
6.2001 International Technology Roadmap for Semiconductors: Executive Summary (Semiconductor Industry Association, San Jose, 2001).Google Scholar
7.Torresola, J., Chiu, C.-P., Chrysler, G., Grannes, D., Mahajan, R., Prasher, R., and Watwe, A., “Density Factor Approach to Representing Impact of Die Power Maps on Thermal Management.” Submitted to IEEE Transactions on Advanced Packaging.Google Scholar
8.Towle, S.N., Braunisch, H., Hu, C., Emery, R.D., and Vandentop, G.J., ”Bumpless Build-Up Layer Packaging,” presented at the ASME Int. Mechanical Engineering Congress and Exposition (IMECE), New York, November 12, 2001.CrossRefGoogle Scholar
9.Viswanath, R., Wakharkar, V., Watwe, A., and LeBonheur, V., Intel. Technol. J. Q3 (August 22, 2000), available from http://developer.intel.com/technology/itj/q32000.htm (accessed October 2002).Google Scholar
10.Chee, C.K., Sterrett, T., LeBonheur, V., De Cesare, L., and He, Y.; in Proc. GlobalTronics Technology Conf. (Singapore) (in press).Google Scholar
11.Skokov, S., Jiang, L., Pantuso, D., and Shankar, S., Intel Assembly Test Technol. J. 4 (Intel Corp. Internal Technical Journal, 2001) p. 254.Google Scholar
12.Zhang, J., Intel Corp. internal technical communication (2000).Google Scholar
13.Jayaraman, S., Koning, P., Hua, F., Chen, T., Gettinger, C., and Clemmons, G., Intel Assembly Test Technol. J. 4 (Intel Corp. Internal Technical Journal, 2001) p. 215.Google Scholar
14.Bohr, M.T. and El-Mansy, Y.A., IEEE Trans. Electron Devices 45 (3) (1998) p. 620.CrossRefGoogle Scholar
15.Allda, S., in Proc. IEEE Int. Interconnect Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 1999) p. 161.Google Scholar
16.Chen, S.-T., Cohen, S., Dalton, T., Della-Guardia, R., Gates, S., Greco, S., Hedrick, J., Huang, E., Krishnan, M., Malone, K., Miller, R., Narayan, C., Nitta, S.V., Purushothaman, S., Rodbell, K., Ryan, J.G., Saenger, K., Simonyi, E., Tyberg, C., and Volksen, W., in IEDM Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2001) p. 23.2.1.Google Scholar
17.Andideh, E., Blaine, J., Block, C., Jin, B., Scherban, T., and Sun, B., in Proc. IEEE Interconnect Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2001) p. 257.Google Scholar