The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). The source region provides a supply of mobile charge when the device is turned “on.” The source is electrically isolated from the drain by the channel region, which is oppositely charged. An insulating oxide layer between the gate and the channel region forms a capacitor. During operation, a voltage is applied to the gate. By applying the appropriate voltage, a conductive layer of charge can be attracted in the channel region at the oxide/silicon interface. This layer of charge acts as a wire that effectively connects the source and drain regions. By changing the voltage on the gate, the conducting layer of charge can be removed. Thus the transistor acts like a switch, with the gate electrode controlling the connection from the source to the drain. These individual switches can be connected to form the basic building blocks for circuit design. These building blocks are used to create the high-performance microprocessors and memory chips in today's computers.

High-purity silicon used for the growth of single crystals is a material with a high resistivity. Small traces of foreign atoms, which are mainly substitutionally dissolved on lattice sites, make the material highly conductive and therefore suitable for electronic applications. The controlled incorporation of extrinsic point defects in silicon is the main task for the production of electronic devices. Homogeneous doping is generally achieved by adding a controlled amount of the dopant element to the silicon melt. However, the fabrication of electronic devices like diodes, transistors, and complex integrated circuits requires spatially inhomogeneous dopant distributions. Control of the inhomogeneous doping profiles demanded by the considerations outlined in the article by Packan in this issue requires a detailed knowledge of the atomic mechanisms of dopant diffusion in silicon, the properties of intrinsic point defects like vacancies (V) and self-interstitials (I), and the interactions among different point defects.

Silicon produced for the microelectronics industry is far and away the purest and most perfect crystalline material manufactured today. It is fabricated routinely and in very large volumes. Many of the advances in integrated-circuit (IC) manufacturing achieved in recent years would not have been possible without parallel advances in silicon-crystal quality and defect engineering. Transition-metal contamination is a case in point. Essentially all practical problems (minority carrier lifetime, metal precipitation, stacking faults, etc.) associated with metal contaminants have largely been solved through advances in crystal purity.

Progress in silicon technology has been phenomenal since the invention of the transistor some 50 years ago. Device performance has improved by at least a factor of a million in every respect. As the minimum feature size on chips decreases toward 0.1 μm, which should be reached on a mass-production scale in a few years, the device yield is becoming ever more sensitive to defects and impurities. Transition metals, particularly iron, nickel, and copper, are the most common and most detrimental contaminants on a process line, and they can be unintentionally introduced in nearly every process step, including ingot growth, wafer handling, ion implantation, wet-chemical cleaning, high-temperature anneals, or oxidation. To avoid yield losses, the silicon industry has to be very strict with respect to metal-contamination levels on the production line. For instance, for iron, the Semiconductor Industry Association (SIA) Roadmap presently specifies 2.5 ϗ 1010 cm−2 as the maximum tolerable surface concentration, decreasing to 5 ϗ 109 cm−2 by 2004.

Semiconductor-grade silicon is one of the most perfect crystalline materials that can be fabricated. It contains less than 1 ppb of unintended impurities and negligible twins or dislocations. Dopants can diffuse in this near-ideal crystal only by interacting with atomic-scale point defects: interstitial atoms or vacancies. These defects migrate through the silicon lattice, occasionally binding with a dopant atom and displacing it by one or more lattice positions.

Simulation of front-end processing is a critical component of integrated-circuit (IC) technology development. Today's electronics are so small that characterization of their material parameters is very difficult and expensive. Simulation is often the only effective tool for exploring the lateral and vertical doping profiles of a modern device at the level of detail required for optimization. Additionally, the cost of fabrication and test lots increases with each technology generation; for this reason, simulation becomes especially costeffective, if it can be made accurate. Increasingly, process simulation is being performed by harnessing a hierarchy of tools. Ab initio and molecular-dynamics (MD) codes are used to generate insight into the physics of individual particle reactions in the silicon lattice. This information can be fed to kinetic Monte Carlo (MC) codes to establish the dominant, critical mechanisms. Finally, traditional continuum codes can make use of this information and couple with the other process steps to simulate the entire process flow. Both MC and continuum codes can be compared with experiment in order to validate the calculations.