Multilevel metallization of very large-scale integrated (VLSI) circuits has become an area of intense research interest as devices are scaled down in order to increase circuit density. As device dimensions approach the submicron regime, reliability becomes more of an issue. Metallization generally requires good conductivity, electromigration resistance, controllable contact performance, corrosion resistance, adherence, thermal stability, bondability, ability to be patterned into a desirable geometry, and economic feasibility.

Aluminum and its alloys have been commonly used as the main metallization materials because they meet most of the metallization requirements for microelectronic devices. Aluminum, however, suffers from major limitations, such as elec-tromigration and stress-voiding induced open-circuit failure. For the development of ultralarge-scale integration (ULSI) for fast-switching-speed devices, the electrical resistivities of aluminum and its alloys are not low enough. As the minimum geometry is scaled down to one-quarter micron, aluminum and its alloys potentially will be replaced by other materials such as Cu, Au, or superconductors for on-chip interconnection.

Since the birth of integrated circuitry about thirty five years ago, microelectronics design and manufacturing technologies have evolved toward higher integration density with smaller design rules. As the semiconductor industry moves into ultra-large-scale integration (ULSI), device geometries continue to shrink into the sub-half-micron region while circuit densities increase to optimize reliability and improve performance. The resulting demands on interconnect technologies necessitate the exploitation of all development avenues: design, materials, and manufacturing.

Emerging sub-half-micron technologies require multilevel metallization (MLM) design schemes that reduce interconnection lengths and lead to lower signal transmission delays and enhanced device speeds. MLM schemes also permit increased device density, due to the ability to use the third (vertical) dimension, and easier signal routing because of higher flexibility in architectural design. These schemes, in turn, demand interconnect metals that can handle the higher current densities resulting from the decreasing size of device features, without the loss of electrical and structural integrity, and deliver the sheet resistance needed to meet performance demands. They also require reliable deposition techniques to successfully fabricate the increasingly complex architectures as lateral feature sizes are scaled down more rapidly than conductor or insulator thicknesses.

Interconnection technology is a key factor in the continual advancement of integrated systems. The rapid increase in device density and circuit complexity through scaling demands a similar increase in the interconnection density. Traditionally, this is achieved by reducing the metal pitch as well as gradually increasing the number of interconnection levels. As the width and spacing of interconnections are scaled down to submicron dimensions at the chip level and micron dimensions at the board level, signal delay, crosstalk, electromigration, and stress-induced migration become important concerns.

Cu holds promise as an alternative metallization material to Al alloy due to its low resistivity and ability to reliably carry high-current densities. Cu has a bulk resistivity of 1.68 μΩ-cm, whereas Al has a bulk resistivity of 2.65 μΩ-cm. The only metal with a resistivity lower than Cu is Ag. Since Cu has a melting point and atomic weight both higher than Al, it is expected to have better resistance to electromigration, although properties such as grain structure and resistance to corrosion at high temperatures may also affect electromigration characteristics.

There is a tremendous demand for improved performance and speed in consumer electronics that is likely to continue as new applications and developments occur. This demand necessitates a reduction in the critical dimensions and an increase in the density of devices in microelectronic circuits. As a result, new materials must be considered for integration into microelectronics technology. In particular, the metal wiring or interconnects that connect different components in silicon-based semiconductor devices is a subject of great interest. As the dimensions of transistors shrink below the 0.5 μm level, their speed will become limited by the delays in the existing interconnect material, Al-Si-Cu alloy (p ~ 3 μΩ cm). Therefore, to avoid problems associated with RC (“resistance/capacitance”) time delays and voltage drops, it will be necessary to construct interconnections of materials that possess lower resistivities, resistance to electromigration and hillock formation, and resistance to diffusion into other materials (see Table I).

A number of materials are possible candidates to replace the Al-Si-Cu alloy, including W, Ag, Au, and Cu. Tungsten has excellent resistance to electromigration and hillock formation, but has higher resistivity compared with the Al-Si-Cu alloy. Thus, applications of W are likely to be found where short interconnection distances are necessary. Silver has the lowest resistivity of all metals, but is easily corroded and diffuses rapidly into many materials used in semiconductor devices. However, some specific applications for silver are viable, such as the formation of contacts on ceramic superconductors. Gold has a lower resistivity than the Al-Si-Cu alloy and is inert to chemical corrosion. As a result Au is used where device reliability is the primary concern-for example, for wiring in GaAs-based semiconductors and electrical contacts in packaging.

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.

Recent interest in copper-based metallization for ultra fast logic devices has stimulated extensive studies on thermal stability issues, as well as the search for novel deposition and etching processes. In copper wiring technology, thermal stability problems include: (1) rapid diffusion of copper into dielectric substrates, (2) low-temperature reaction with most near-noble metals and their silicides, (3) the susceptibility of copper to oxidation, (4) poor adhesion characteristics of copper on most dielectric materials, and (5) thermal-stress-induced void formation and cracking. The basic issues have been summarized in a recent review.

When copper is in contact with a silicon substrate, copper can diffuse into active regions of devices where it becomes a recombination-generation center. In addition, copper forms the silicide Cu3Si by reacting with the substrate at temperatures less than 200°C. After the formation of the Cu3Si phase, the underlying silicon in the Cu3Si/Si structure is readily oxidized even at room temperature. In the case of copper in contact with silicon dioxide under bias thermal stress (BTS), copper is found at the SiO2/Si interface under a positive electric field. Copper diffusion in doped glass, e.g., phosphosilicate glass and silicon nitride films, is a factor at temperatures below 400°C.