This paper presents a design methodology for a broadband high-efficiency power amplifier (PA). The large available impedance space of the extended continuous Class-GF mode is employed. A novel output matching network of the PA consisting of a rectangular double transmission line structure is proposed to meet impedance requirements. To validate the effectiveness of this structure, a high-efficiency PA operating in 0.8–3.0 GHz is designed using a CGH40010F GaN transistor. The measured results demonstrate that the drain efficiency falls within the range of 63.2%–71.9%, the output power varies from 40.2 to 42.2 dBm, and the gain ranges from 9.4 to 11.3 dB within the frequency band of 0.8–3 GHz. The realized PA exhibits an extremely competitive relative bandwidth of 115.8%.

Worldwide adoption of 5G mobile devices has been one of the main driving engines behind semiconductor industry. Since the initial release in 2020, 5G-enabled devices have surpassed the market penetration of 3G/4G smartphones. 5G brings higher data capacity, low latency, and new applications. These are possible due to lower feature nodes such as FinFET 3 nm/5 nm but also due to improvements of the 5G radio frequency (RF)front-end circuitry. This paper presents 5G RF front-end architectures with novel circuits and measurement details which will be part of future 5G advanced and 6G mobile devices and are easier to be controlled using digital circuitry. The paper presents an envelope-controlled power amplifier (PA) principle, along with a novel simplified calibration architecture designed for 5G/5G+ operating under 6 GHz, as well as for frequency range 2 millimeter-wave PAs. An earlier version of this paper was presented at the 2023 53rd European Microwave Conference and was published in the Proceedings [Balteanu F, Thoomu K, Pingale A, Venimadhavan S, Sarkar S, Choi Y, Modi H, Drogi S, Lee J and Agarwal B (2023) Enabling RF circuit techniques for 5G and beyond In 53rd European Microwave Conference (EuMC), Berlin, Germany, 22–25].

This paper proposes a design method for designing a wideband filtering power amplifier (PA) based on terminated coupled line structure (TCLS). This method generates four transmission zeros and three transmission poles by loading stepped impedance resonator and short-circuit stubs on the four ports of TCLS, which greatly optimizes the in-band return loss and stopband suppression of the output matching network. In addition, the effective suppression of the second harmonic also increases the efficiency of the PA. In order to verify the effectiveness and superiority of this design method, a wideband bandpass filtering PA is designed and manufactured in 2.9–3.7 GHz. Measurement results show that the saturated output power is from 40.1 dBm to 41.2 dBm, the drain efficiency is greater than 60.3%, and the gain is 10–11.2 dB.

This paper presents an integrated power amplifier (PA) following the orthogonal load-modulated balanced amplifier (OLMBA) topology. The fixed-phase prototype in this paper is implemented with 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon-on-insulator (FDSOI) process. The proposed PA operates at 26 GHz frequency range, where it achieves 19.5 dBm output power, 16.6 dB gain, 15.7% power added efficiency, and 18.3 dBm output 1-dB compression point ($P_{\rm 1\,dB}$). The PA is also tested with high dynamic range modulated signals, and it achieves, respectively, 11.4 dBm and 4.9 dBm average output power (Pavg) with 100 MHz and 400 MHz 64-QAM third-generation partnership project/new radio frequency range 2 signals, and 14 dBm Pavg with 0.6 Gb/s (120 MHz) single carrier 64-QAM signal, measured at 26 GHz and using −28 dBc adjacent channel leakage ratio and −21.9 dB (8%) error vector magnitude as threshold values. The proposed OLMBA is also compared to a stand-alone quadrature-balanced PA. Modulated measurements show that the stand-alone quadrature-balanced PA has better linearity in deep back-off, but the OLMBA has better efficiency.

In this paper, a realization method for high-efficiency broadband power amplifier (PA) based on split-ring resonator (SRR) second harmonic output matching network (SHOMN) is presented. The SRR is composed of double rectangular rings, and it can flexibly match the second harmonic components to the high-efficiency impedance region in the Smith chart in a wide frequency band. Besides, the impedance transformation characteristic of SRR is derived, and the optimal output impedance is converted from the transistor drain to the output of SHOMN for accurate fundamental matching. For validation, a PA operating in 1.2–3.0 GHz is designed and fabricated for a 10-W GaN transistor. The measurement results show that the maximum efficiency can reach 78.3%; meanwhile, the average saturated output power is 41.0 dBm.

Worldwide adoption of fourth-generation wireless (4G) long-term evolution (LTE) smartphones and the actual transition to fifth-generation wireless(5G) is the main driving engine for semiconductor industry. 5G is expected to reach high data rate speeds (1 Gbps) and low latency (<1 ms). 5G requires more RF bandwidth and therefore an increase in the number of components such as RF switches, acoustic filters, and power amplifiers integrated in few RF front-end modules. Also, there is an increase in the number of RF radio transmitters and receivers operating at the same time. This paper presents new architecture elements for 5G RF front-end modules. Circuit details and measurements are presented to reduce the RF noise, improve the efficiency, and help the coexistence of multiple radio transmitters. These circuits will help extend the 5G applications with radar-like sensing applications, remote medicine, and autonomous driving.

A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmission line on the other side. This configuration is attractive because of its design simplicity and easy fabrication. Compared with the conventional techniques that utilize capacitors and inductors instead of the shunt 90° transmission line, the proposed LO power splitter can alleviate the issue of process variation. The demodulator demonstrates an IRR lower than −40 dBc from 37.5 to 41.5 GHz. In addition, conversion gain is 1.3 ± 0.9 dB from 33 to 41 GHz with 6 dBm LO power. The total direct current power consumption is 78 mW from 1.0 V supply voltage. At the modulation scheme of 4096-QAM, the proposed demodulator demonstrates 1.7% (−35.1 dB) error vector magnitude (EVM), which is very close to the EVM measurement floor 1.6% (−36 dB) of our millimeter-wave signal analyzer.

In this paper, two high efficiency monolithic microwave integrated circuits (MMICs) are demonstrated using NANOTAM's in-house Ka-band fabrication technology. AlGaN/GaN HEMTs with 0.2 ${\rm \mu}$m gate lengths are characterized, and an output power density of 2.9 W/mm is achieved at 35 GHz. A three-stage driver amplifier MMIC is designed, which has a measured gain higher than 19.3 dB across the frequency band of 33–36 GHz. The driver amplifier exhibits 31.9 dB output power and 26.5% power-added efficiency (PAE) at 35 GHz using 20 V supply voltage with 30% duty cycle. Another two-stage MMIC is realized as a power amplifier with a total output gate periphery of 1.8 mm. The output power and PAE of the power amplifier are measured as 3.91 W and 26.3%, respectively, at 35 GHz using 20 V supply voltage with 30% duty cycle. The high efficiency MMICs presented in this paper exhibit the capabilities of NANOTAM's 0.2 $\rm\mu$m AlGaN/GaN on SiC technology.

A time-domain duplexing radio frequency (RF) front-end with integrated antenna switch, power amplifier (PA), and low noise amplifier (LNA) was developed aiming for fifth-generation communication (5G) applications covering 24–28 GHz frequency range. Antenna switch utilizes pre-existing LNA input matching network together embedded with grounded shunt transistor switch to provide sufficient isolation of receive side from PA. Respectively, high impedance of off-state PA is assumed to achieve acceptable receive performance. Resulting output power is 13.6 dBm with 15 dB of peak small-signal gain at 28 GHz. Maximum average channel power was 4.8 dBm with 100 MHz 64-QAM OFDM signal within 5G adjacent channel power ratio and error vector magnitude specifications. Receive (RX) front-end achieves 5 dB noise figure at 24 GHz and 7 dB of peak gain. Performances of amplifiers degraded only by 2 dB from switch integration. The front-end dissipates 183 and 4.6 mW of power in transmit and receive mode, respectively. The simplistic design method minimizes cost both in circuit area (only 0.19 mm2) and design time making this front-end an attractive alternative in massive phased array applications using 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon on insulator process.

This paper discusses the design steps and experimental characterization of a monolithic microwave integrated circuit (MMIC) power amplifier developed for the next generation of K-band 17.3–20.2 GHz very high throughput satellites. The technology used is a commercially available 100-nm gate length gallium nitride on silicon process. The chip was developed taking into account the demanding constraints of the spacecraft and, in particular, carefully considering the thermal constraints of such technology, in order to keep the junction temperature in all devices below 160°C in the worst-case condition (i.e., maximum environmental temperature of 85°C). The realized MMIC, based on a three-stage architecture, was first characterized on-wafer in pulsed regime and, subsequently, mounted in a test-jig and characterized under continuous wave operating conditions. In 17.3–20.2 GHz operating bandwidth, the built amplifier provides an output power >40 dBm with a power added efficiency close to 30% (peak >40%) and 22 dB of power gain.

This paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.

A novel, broadband, nonlinear behavioral model, based on support vector regression (SVR) is presented in this paper. The proposed model, distinct from existing SVR-based models, incorporates frequency information into its formalism, allowing the model to perform accurate prediction across a wide frequency band. The basic theory of the proposed model, along with model implementation and the model extraction procedure for radio frequency transistor devices is provided. The model is verified through comparisons with the simulation of an equivalent circuit model, as well as experimental measurements of a 10 W Gallium Nitride (GaN) transistor. It is seen that the efficiency prediction throughout the Smith chart, for varying fundamental and second harmonic loads, across a wideband frequency range, show excellent fidelity to the measured results. Device dc self-biasing is also modelled to allow prediction of power amplifier (PA) efficiency, which is shown to be highly accurate when compared with corresponding measured data. Finally, a class-J PA is constructed and measured across the frequency with a large-signal input tone. The resulting measured and modelled values of key PA performance figures are shown to be in excellent agreement, indicating the model is suitable for broadband PA design.

This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Each of the various methods for mixed-mode load-pull measurements, which can be found in literature, has its own advantages and disadvantages. In this publication, we analyze two of the most commonly used setups and a third setup of which we provided an initial treatment in a previous publication. We investigated the impact of 180° hybrids on the tuning capabilities of a mixed-mode load-pull system. Furthermore, we provide a rule-of-thumb to easily estimate this impact using only some specifications of hybrids. For all analyzed setups, we use measurement results to show that the tuning range of the newly proposed setup is superior compared to the other setups, though hardware effort and tuning complexity are greater.

This paper presents a novel GaN-based digital outphasing power amplifier (PA) for the 800 MHz range. The PA reaches a maximum output power of 5.8 W at 30 V final-stage (FS) drain supply voltage. A novel output combiner circuit is used and efficiency is improved by resonant commutation of the FSs and optimized driver circuits for the two GaN push-pull FSs. 3D electromagnetic simulation of output network has been conducted to extract an equivalent circuit model and to access full information in terms of functionality and broadband impedance characteristics for optimized outphasing operation in the final design. Measured total efficiencies (ηtot) of 59 and 25% at 0 and 10 dB power back-off are achieved, respectively, fitting the simulation quite well. The proposed digital outphasing module is a promising candidate for fully digitized base-station architectures in future wireless communications.

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

In this paper, the concept of load-modulated power amplifiers (PAs) is studied. Two GaN-HEMT power amplifiers (PAs), targeted for high efficiency at maximum and output back-off (OBO) power levels, are designed, implemented, and tested across 1.8–2.2 GHz. The load modulation in the first design is realized by tuning the shunt capacitors in the output matching network. A novel method is employed in the second design, where barium–stronrium–titante is used for the realization of load modulation. The large-signal measurement results across the desired band show 59–70% drain efficiency at 44–44.5 dBm output power for both designs. Using the available tunable technique, the drain efficiency of the PAs is enhanced by 4–20% at 6 dB OBO across the bandwidth.

In this work, the design of the wideband millimeter-wave power amplifier for multiband communication is presented. In order to achieve compact, simple and robust design, a differential cascade transformer-coupled topology is used. The amplifier is implemented in 90 nm low-leakage CMOS technology and achieves 3 dB bandwidth of 8 GHz (from 60 to 68 GHz) and a peak gain of 18 dB. The PO1dB is better than 5 dBm from 58 to 80 GHz, and peak output power is 11.9 dBm with 1 dB flatness from 62 to 77 GHz. The chip consumes an area of 0.25 mm2 including bond pads and DC current of 125 mA from a 2.2 V supply.

In this paper we present the design and realization of a high-power amplifier in grounded coplanar transmission line technology using AlGaN/GaN dual-gate High electron mobility transistors (HEMTs) with a gate-length of 100 nm to achieve a high gain per stage and high output power. A large-signal model was extracted for the dual-gate HEMT based on the state-space approach. For the fabricated dual-stage amplifier a continuous-wave saturatedoutput power of up to 24.8 dBm (0.84 W/mm) was measured at 63 GHz for 20 V drain bias. A small-signal gain of more than 20 dB was achieved between 56 and 65 GHz.

This paper shows the contribution of slow-wave coplanar waveguides on the performance of power amplifiers operating at millimeter-wave frequencies in CMOS-integrated technologies. These transmission lines present a quality factor Q two to three times higher than that of the conventional microstrip lines at the same characteristic impedance. To demonstrate the contribution of the slow-wave transmission lines on integrated millimeter-wave amplifiers performance, two Class-A single-stage power amplifiers (PA) operating at 60 GHz were designed in standard 40 nm CMOS technology. One of the power amplifiers incorporates only the microstrip lines, whereas slow-wave coplanar transmission lines are considered in the other one. Both amplifiers are biased in Class-A operation, drawing, respectively, 22 and 23 mA from 1.2 V supply. Compared to the power amplifier using conventional microstrip transmission lines, the one implemented with slow-wave transmission lines shows improved performances in terms of gain (5.6 dB against 3.3 dB), 1 dB output compression point (OCP1dB: 7 dBm against 5 dBm), saturated output power (Psat: >10 and 8 dBm, respectively), power-added efficiency (PAE: 16% instead of 6%), and die area without pads (Sdie: 0.059 mm2 against 0.069 mm2).