This paper is overviewed the recent progress on GaN HEMTs. High power, high frequency and high efficiency performance are reported. In addition, the results about long-term reliabilities and good manufacturability demonstrate that GaN HEMTs are ready for mass production.

The impurities segregated at the grain boundary of ZnO grains, such as Bi2O3, are important factor to obtain the nonlinear voltage-current (V-I ) characteristics of a Bi-added ZnO varistor. The deterioration of V-I characteristics progresses with voltage application. It has been reported that one of the reasons for this deterioration is the movement of oxide ions and interstitial Zn2+ ions across grain boundaries and around the neighborhood of grain boundaries. Thus, the mobility of ions and the pathway of the current formed by voltage application strongly correlate with the structure of grain boundary, such as the crystal orientation of ZnO grains, the phase of Bi2O3 at the grain boundary, and segregated grains. In the present studies, the structure of grain boundary for the ZnO varistor has been evaluated by composition images obtained from energy dispersive X-ray spectrometry (EDS) with scanning electron microscope (SEM) or with transmission electron microscope (TEM). However, the elemental mapping obtained from EDS with SEM is low resolution and the distribution of elements is obscure. Furthermore, the observation of varistor with TEM is difficult because the sample used for TEM needs precise processing. On the other hand, a composition image with high contrast of tone can be easily obtained using back-scattered electron (BSE) detector with SEM, although BSE detector is lack in the quantitative analysis. In this study, to clarify the microscopic distribution of impurities at the grain boundary with simple method, we observed the fractured surface of ZnO varistor using BSE detector with SEM. For the fractured surface, two types of fracture exist; grain boundary fracture and transcrystalline fracture. The microscopic distribution of impurities can be obtained by observing the surface of grain boundary fracture. The characteristics of ZnO varistor deeply correlate with the state of impurities at the grain boundary such as Bi2O3. To clarify the distribution of these impurities, the fractured surface of Bi-Mn-Co-Sb-added ZnO varistor was observed using SEM, EDS, and BSE detector. It was found that the deposit of Bi2O3 as additive had two types of shape on the surface of grain boundary fracture; spot-like and sheet-like, for Bi-Mn-Co-Sb-added ZnO varistor. With dissolving SiO2 in Bi2O3, the surface tension of Bi2O3 decreased and the sheet-like deposit of Bi2O3 increased, while the spot-like deposit of Bi2O3 decreased. Moreover, when the sample was annealed at 700°C, the surface free energy (surface tension) decreased because Zn2+ and Bi3+ were speculated to become the compound such as Bi7.65 Zn0.35 O11.83 and move to the triple point or line.

In this paper, we proposed a phase-change random access memory (PCRAM) cell with a self-insulated structure (SIS), which is expected to have better thermal efficiency than the conventional structures. 3-D finite element simulation is used to study the most power consuming RESET process for both SIS and conventional normal bottom contact (NBC) cells driven by a MOSFET. Instead of programming current, power consumption is investigated to give a more fundamental comparison between the two structures. Thermal proximity effect for both kinds of cells is directly analyzed by simulating a 3×3 device array. The potential slow-quenching issue of SIS is also discussed.

The properties of Ta2O5 thin films with respect to different underlayer stack have been investigated. At first, a set of samples were produced at various conditions as an underlayer of Ta2O5 film deposition. Then, Ta2O5 films were grown using a MOCVD method with Ta(OC2H5)5 pre-curser at 440 °C. The Process parameters for Ta2O5 films were remained same through the preparation of the sample set. The results were analyzed using various methods including thickness measurement, SEM, stress measurement, X-ray diffraction (XRD), and electrical property measurements. Different grain structures and growth rates were observed with respect to the different underlayer preparation condition mainly as a function of deposition temperature. The deposition rate varied from 0.6 Åsec to 1.8Åsec depend on different underlayer. Crystalline Ta2O5 films with large-grain-size were obtained on Aluminum/TiN underlayer stack. Films with crystalline structure show better leakage current characteristics than the amorphous one.

By means of two-point-probe Spreading Resistance (SR) analyses, the formation and evolution of hydrogen-related and vacancy-related donor and acceptor states were studied in helium implanted and subsequently hydrogen plasma-treated n-type Float-Zone (FZ) silicon wafers. He-implantation was carried out at 3.75 MeV, applying fluences of 1×1014 cm-2 and 2×1013 cm-2. After 15-min post-implantation H-plasma exposures at substrate temperatures between 350 °C and 500 °C, distinct surplus doping profiles were observed in the subsurface layers of the treated FZ Si samples down to about 20 μm depth. Enhanced donor concentrations could be observed as well acceptor-like states, at least partially compensating for the initial n-type doping, so that even buried p-type layers can be created under appropriate process conditions. The nature of the defect complexes that were responsible for the observed doping profiles in the subsurface layer of the studied samples will be discussed.

Samarium oxide (Sm2O3) and samarium gallium oxide (SmxGa1-x)2O3 have been proposed as candidate dielectric materials for the development of gallium arsenide (GaAs) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology. Growth of thin (20nm-50nm) Sm2O3 and (SmxGa1-x)2O3 layers on GaAs substrates via plasma-assisted molecular beam epitaxy (MBE) has been performed using a range of growth temperatures and samarium cell temperatures. X-ray photoelectron spectroscopy (XPS) of the deposited films showed evidence of unbonded Sm metal in the films which decreased with decreasing Sm cell temperature, but was relatively independent of substrate temperature. Stoichiometry of the oxide was found to be independent of substrate temperature, but increased in oxygen to metal ratio as the Sm cell temperature was decreased. Decreasing the Sm cell temperature also suppressed the formation of the monoclinic phase and promoted the growth of the cubic phase. Films grown at higher (500şC) temperature showed the presence of a crystalline interface, but relatively high surface roughness and the presence of multiple crystalline phases. Current-voltage analysis of one hundred micron diameter MOS diodes showed breakdown fields at 1 mA/cm2 of up to 4.35 MV/cm. Breakdown field was found to decrease with increasing Sm unbonded metal content in the films. The effect of stoichiometry and phase distribution on the interface state density (Dit) and capacitance-voltage behavior of MOS diodes was also investigated.

Titanium and cobalt silicides have long been used as gate electrode materials for very large-scale integrations (VLSI) circuits. As scaling has pushed the industry to quarter micron technologies and below, cobalt has become the material of choice for forming silicides, since it can maintain its low resistivity on much narrower line widths. Oxidation of the cobalt film is a concern during silicide processing, as the cobalt oxide will not be removed during the cobalt etch step. To protect against the oxidation of the cobalt layer during the silicidation process, the reaction is conducted underneath a titanium nitride (TiN) capping layer. Variations in the TiN capping layer thickness were investigated to determine the affect on oxygen sensitivity of the cobalt silicide process. A strong correlation was found to the thickness of the TiN-capping layer, to the oxygen concentration required to oxidize cobalt during the silicidation process.

The effect of BCl3 and BCl3/Ar pretreatment on Cl2/Ar and Cl2/Ar/BCl3 dry etching of AlN is investigated using inductively coupled plasma reactive ion etching. The native AlN oxide can be effectively removed by a short exposure to BCl3 or BCl3/Ar plasma. Compared to the chlorine based plasma etching, BCl3/Ar is found to have the highest etch rate for both AlN and its native oxide. Following removal of the native oxide, Cl2/Ar/BCl3 plasma etching with 15% BCl3 fraction results in a high etch rate ˜ 87 nm/min and modest increases in the surface roughness.

Interface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency.

In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window.

Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).

The electronic current-voltage characteristics of a nanotransistor is studied. The nanotransistor is assumed to consist of a quantum dot active region connected to the source and drain wires and also attached to a gate. The electric current is shown to be influenced by the coupling of electrons to the longitudinal optical phonons, namely, by the up-conversion of the electrons to the higher excited states in a quantum dot, due to a nonadiabatic effect of the lattice vibrations. In the nanotransistor with asymmetric source and drain contacts the up-conversion leads to a spontaneous electric current, or to a spontaneous voltage between the electrodes. We remind existing experiments which might be related to the effect considered.

We present experimental results on the effect of strain on hole transport in InGaAs quantum well (QW) structures. Indium content was varied from lattice matched to high compressive stress in InGaAs/InP QW and the transport properties were analyzed at various temperatures (T = 77-300 K) using Hall measurements. The effect of QW thickness (4-20 nm) on hole transport is also presented. The current best results include room temperature mobility and sheet resistance of 390 cm2/V-s and 8500 Ω/sq., respectively. It was observed that the mobility had a T-1.8 dependence indicating similar scattering mechanism in almost all of the samples with prominent mechanism being due to interface and barrier scattering. Further optimization of p-channel for InGaAs CMOS needs to be performed using the above results as guidelines.

The ZnO TFTs have attracted much attention as key component for flexible displays because they can be fabricated on plastic substrates at low temperature and exhibit good electrical performance. However, the ZnO films are polycrystalline with grain boundaries even if formed at room temperature, which deteriorate the uniformity of TFT characteristics. A few research groups have reported high performance amorphous indium-gallium-zinc oxide TFTs to solve the native problem of nonuniformity of ZnO TFTs. However, there are few researches on the process parameter effects on the variation of a-IGZO TFT characteristics. In this study, we focus on the effect of the source/drain overlap length on threshold voltage(VT) of a-IZO TFTs with differentiating channel deposition method. The experimental structures for this work are bottom-gated TFTs with a-IGZO channel that were deposited by RF and DC magnetron sputtering on glass. RF and DC sputtering were carried out by magnetron power density of (1.4 W/cm2)/ (2.0 W/cm2) in Ar/O2 gas ratio of (65/35)/(72/28), and the entire gas pressure were 5.0 mTorr and 3.4 mTorr. The width/length(um/um) of device was split to 10/7,10/10,10/30,10/50. Each of the patterns has seven source/drain overlap length: -3um,-2um,-1um,0um,1um,2um,3um. We extracted VT of RF and DC through the VG-ID curve. There are significant VT difference in both RF and DC according to the overlap length: VT of DC(RF) is 1.31(0.74)V at W/L=10/50 and 10.21(5.74)V at W/L=10/30. VT increases definitely where less than 1um overlap length and short channel TFT is more influenced by overlap length, which is more severe in RF group. We calculated total channel resistance (RT) from VD-ID curve. RT of devices with the positive overlap can be expressed by RT, Postive=Rch+Rc. Here, Rch is net channel resistance which becomes smaller when channel length decreases and Rc is contact resistance. RT with negative overlap, is RT, Negative=Rch+Rc+Roffset. Roffset is offset resistance formed by negative overlap and can be extracted by subtracting RT, Postive from total RT, Negative. The RT of DC(RF) at offset channel length of-1um,-2um,and-3um is 4.43105(2.7 106)cm, 1.17 106(3.48 106)cm, and 1.46 106(4.73 106)cm, respectively(W/L=10/10um) RF group which shows inferior electrical characteristics such as lower mobility and larger subthreshold slope to DC, have larger Roffset than the DC. This implies that the devices require a bit of positive source/drain overlap length for uniform VT especially when the channel resistance is high. But Overlap region causes difficulties in the device area to be miniaturized. In summary, as the source/drain overlap length decreases to negative value, the threshold voltage of a-IGZO TFTs increases sharply and these tendency strongly depends on a-IZO film quality, which means the overlap length is very important control parameter of a-IGZO TFTs for the uniform threshold voltage especially when the channel resistance is high

Performances of AlGaN/GaN HFETs have much improved recently and very high potential of this hetero- structure for high power and high frequency electronic devices has been verified. Application of new device technologies such as field plate, recessed gate, digital pre-distortion circuit and dual field plate was essential to realize such high device performances both at 2 GHz, 5GHz and 26 GHz. However, practical requirements on the quality and structure of these material systems for production of these devices are still not clear. Extensive studies on correlation among material quality, device performance and reliability were investigated under Japanese NEDO project. Firstly, this paper reviews recent progress of the performances of high power and high frequency AlGaN/GaN HFETs. Then, several interesting results which suggest practical requirements on material quality and structure will be discussed based on our extensive characterization studies in terms of device performances and reliabilities.

Nitride based Distributed Bragg Reflectors (DBRs) have several important applications in current nitride based optoelectronic devices. DBRs can be implemented in resonant cavity light emitting diodes (RCLEDs) to improve light extraction and obtain a more directional emission and in vertical cavity surface emitting lasers (VCSELs) to achieve a lower threshold current. Due the large contrast in refractive index, AlN/GaN DRBs are practical for obtaining high reflectivity and wide bandwidth using relatively few periods. Cracking of the samples is typical for AlN/GaN DRBs due to the tensile strain which results from the 2.4% lattice mismatch and to the difference in thermal expansion coefficients. In addition to cracks, v-shaped defects may also arise in the surface due to surface undulation from stored elastic misfit strain or from threading dislocations that result in scattering and diffraction. Several techniques to reduce the number of cracks and defects have been investigated to obtain smooth surface morphology and high reflectivity, e.g. superlattices to reduce the strain or the growth of AlInGaN/GaN DBRs that offer less lattice mismatch but also lower refractive index contrast. In this work, results of the use of Indium (In) as a surfactant in Metal Organic Vapor Phase Epitaxy (MOVPE) will be discussed. This study addresses AlN/GaN DBR structures designed for peak reflectivity around 465 nm. During the AlN layers’ growth, trimethylindium was introduced to the system and resulted in a reduction of surface cracks. Results of growths at In flow rates are reported and discussed.

In this work we study the defects responsible for the degradation of high power AlGaAs based laser bars. The mirror and cavity degradations are studied by spectral cathodoluminescence (CL) imaging. Following the analysis of the CL images the main defects generated during the laser operation are revealed, both facet and intracavity defects are observed. A thermomechanical model is used to describe the very beginning of the defect formation. The defects are formed by a local plastic deformation induced by local heating at defects.

To improve the IPD reliability of NAND flash memory, plasma oxidation was introduced as the post-treatment process of ONO (Oxide/Nitride/Oxide) IPD. The LP-CVD SiO2 modified by plasma oxidation showed the excellent electrical properties. e.g., low leakage current, high breakdown voltage etc. By the analysis of Tof-SIMS and XRR, we could observe the several changes of physical characteristics such as the reduction of impurities (H, N etc.), the increase of oxide density, and the improvement of oxide surface roughness. We found out the appropriate treatment condition to be able to densify oxide layer without the addition of ONO Equivalent Oxide Thickness (EOT). The LP-CVD SiO2 prepared by plasma oxidation was used for the ONO IPD of 50nm NAND flash device and also compared with the conventional LP-CVD SiO2 in the aspect of the IPD reliability.