The threshold voltage (VT) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the absence of a drain bias (VG=15V, VD=0V), the threshold voltage (VT) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (VG=15V, VD=20V), the VT shifts of asymmetric TFTs were less than symmetric TFT. The VT shifts of ‘L’ and ‘J’ shaped TFT were 0.29V, 0.24V respectively, while the VT shift of ‘I’ shaped TFT was 0.42V.

The less VT degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less VT degradation compared with the symmetric TFT.

Compared to plastic, from the view point of ultra low temperature poly-Si (ULTPS) processes for realizing flexible active matrix organic light emitting diode (AM-OLED) display, SSF offers high thermal resistance and chemical stability, and lithography stability. As SSF is stiffer than plastic film, SSF is expected to reduce stress which originates from difference in coefficient of thermal expansion. However, SSF substrate itself also bears surface roughness problem, which necessitates an appropriate planarization step. Also to fully integrate both the drive circuits and the pixel thin-film transistor(TFT)s in a monolithic complementary metal-oxide-semiconductor (CMOS) technology high mobility is required, calling for poly-Si usage.

We will deal with the planarization process, and then address various processing issues. Especially, we will demonstrate our successful SLS of Si on SSF substrates. Finally we show the device performances. All fabrication temperatures were kept below 200 oC to meet a ULTPS process.

Due to the rolling process for manufacturing foils, the SSF surface is rough. We have measured average roughness of 500 nm, respectively. With benzocyclobutene (BCB), we have successfully planarized the surface with average roughness was less than 0.5 nm.

Our TFT's active layer was obtained by laser crystallizing amorphous Si (a-Si) films. To obtain a high quality gate dielectric film, we formed a SiO2 film using an O2 plasma treatment on the surface of the poly-Si film and then deposited Al2O3 film by plasma enhanced atomic layer deposition. Then gate metal was deposited and patterned. Source and drain regions were p+ doped by ion implantation to form a self-aligned gate structure. We have used SiNx film as interlayer dielectrics.

Briefly we discuss a practical approach for realizing SLS on a SiO2 buffer. The Si-on-SiO2 layer stacking is energetically unstable. Should have not controlled the heat during laser crystallization, liquid Si would recede to expose the SiO2 layer. Dewetting is suppressed by adjusting the buffer density, and densifying the a-Si film. To implement the SLS, we have optimally conjugated the densities of the buffer film and the a-Si film to produce Si grains with sizes of ~6 ¥ìm on a BCB planarized SSF.

Our p-channel TFT transfer performance exhibits a field effect mobility (¥ì) of 95 cm2/Vs, a threshold voltage (Vt) of -3 V and a sub-threshold swing(S-S) of 0.5 V/dec.. The off-current level is ~ 10 pA at drain voltage (Vd) of -1V and the Ion/Ioff is 106 . Especially our stable Vt consents to the electrical stability for driving displays. This feature might be attributed to the improved interface between the active layer and the gate dielectrics by plasma oxidation.

This paper investigates the robustness of the thermally stimulated current technique as a method to determine the density of states distribution in thin film semiconductors under a wide range of conditions. Numerical simulation is used to solve the non-linear time-dependent rate equations for free and trapped charge in systems with continuous and structured DOS profiles. We explore the derivation of energy and density scales from temperature and conductivity data. We examine for these systems the limits of the method's apparent immunity to varying conditions of strong and weak retrapping, and investigate the corrections required for variations in carrier lifetime with temperature.

A technique for enlargement of grain size were shown and a technique for location controlled super lateral growth (SLG) grain in excimer laser annealing (ELA) were proposed and realized. In the technique for grain size enlargement, the grain size was enlarged to 10£gm that is more than 10 times larger than that in conventional method(~0.8£gm). The proposed sample structure was Si film/light absorptive film/Glass structure with applying the laser light from the back side of glass substrate. Time resolved(~1ns) optical measurement (TROM) revealed that the melt duration of Si film was increased to 800ns that is also 10 times longer than that in conventional method. As for the grain location control technique, a new method contains pre seeding process and post growth process were proposed and realized. In the pre seeding process, micro light beam(£g-light beam) was exposed to Si film to form a grain within the crystallized spot. £g-light beam was formed by micro-lens-array(MLA). After post growth process, single grain array with the diameters of 6£gm was formed in a period of 10£gm.

The epitaxial thickening of a thin polycrystalline Si (poly-Si) film (seed layer) is a promising approach to realize an absorber layer of a poly-Si thin-film solar cell on glass. Such cell concept combines the benefits of crystalline Si and the high potential for cost reduction of a thin-film technology. Here, we discuss the influence of post-deposition treatments on the properties of absorber layers grown by electron-cyclotron resonance chemical vapor deposition (ECRCVD) and the solar cell performance, respectively. After the absorber growth and prior to the emitter deposition, defect annealing was used to improve the structural quality of the absorber layers and to increase the doping efficiency. For this, we used rapid thermal annealing (RTA) processes as well as thermal annealing in a conventional quartz furnace. In order to avoid damaging of the glass, only short annealing times (up to 400 s) were applied at temperatures of up to 950 °C. Defect passivation treatments were carried out at temperatures of about 350 °C to passivate the remaining defects in the films by hydrogen. The impact of both treatments on the solar cell parameter will be discussed. Excellent VOC's of up to 361 mV were achieved without hydrogenation showing the high potential of ECRCVD-grown absorbers. Applying both treatments resulted so far in an increase of VOC of about 400 mV. Because of the fact, that both post-treatments (particularly hydrogenation) are still not yet optimized, further improvements can be expected.

In this paper, the potential of hot-wire chemical vapor-deposited (HWCVD) microcrystalline silicon (μc-Si) for use in solar cells is explored. Incorporation of the material in the current-limiting bottom cell of two tandem cells on plain stainless steel resulted in FF values as high as 0.77, which is much higher than the highest single junction FF. A combination of experiments, calculations and computer simulations was employed to identify causes for the observed high tandem cell FF values. Both the light intensity and the spectral composition of the bottom cell illumination in a tandem were found to contribute to an increase of the bottom cell FF. The fact that the operational voltage of a tandem cell is higher than that of the current-limiting subcell, was calculated to lead to a tandem FF that can be far higher than that of the limiting cell. Com-puter simulations with the AMPS computer code show that the current mismatch in a tandem cell reduces the recombination in the current-limiting cell, possibly by slightly enhancing the internal field of that cell. Use of a 1.5 μm ìc-Si:H hot-wire deposited absorber layer in a single junction cell on a textured back reflector yielded a Voc, FF and Jsc of 0.543 V, 0.656 and 23.60 mA/cm2, respectively, which combine to an 8.4 % record efficiency for μc-Si single junction n-i-p cells with a hot-wire intrinsic layer.

Image sensors based on thin-film on CMOS technology (TFC) have been developed. In this approach, amorphous silicon (a-Si:H) detectors are vertically integrated on top of a CMOS readout chip so as to form monolithic image sensors. In order to reduce as far as possible the dark current density (Jdark) of the TFC sensors, we have focused on analyzing and understanding the behavior of Jdark in this type of detectors. Edge effects along the periphery and at the corners of the pixel, due to the non planar configuration of the vertically integrated photodiodes, are found to be responsible for an increase of the dark current. A new and adapted solution for the minimization of Jdark is proposed, which combines the use of a metal-i-p a-Si:H diode configuration with a deposition on top of an unpassivated CMOS chip. Values of Jdark as low as 12 pA/cm2 at a reverse polarization of V = -1 V are measured on such TFC sensors.

Hydrogenated amorphous silicon (a-Si:H) films of high and low hydrogen content were deposited directly on molybdenum, carbon-coated TEM grids by hot-wire chemical vapor deposition. The material was annealed at 600°C and 630°C for variable times to achieve various degrees of crystallinity. The films thickness of 100-nm allowed characterization by TEM without additional thinning. The grain growth in such thin films is nearly two-dimensional, allowing clear identification of crystalline and amorphous regions. Thus, the crystalline volume fraction can be tracked by simple image-processing methods. The evolution of crystallization by grain nucleation and growth for these films is accurately described by classical phase-change kinetics. Analysis of the randomly distributed grains at early stages of crystallization also provides the average areal grain number density and grain size. From the image analysis, we determine the grain nucleation rate and the grain growth velocity. The final grain size is then estimated by extrapolation to the fully crystallized state, assuming the kinetic parameters remain constant after the onset of crystallization.

A homogeneously mixed phase of carbon and 10% nickel yielding amorphous carbon-nickel composite (a-C-Ni) films is prepared by an excimer UV pulsed laser ablation. Conductivity study of these films shows a nearly activated conduction. Also a saturation of conductivity below a temperature of 25 K explains the presence of an additional density of states at the Fermi level in these samples. Our experiments demonstrate a very different behaviour of electronic properties of these novel materials compared to undoped diamond-like carbon (DLC) films, which was directly confirmed using valence band spectroscopy.

Stacked ITO/(a-SiC:H)pinpi /(a-Si:H)i'sn/ITO color sensitive detectors are analyzed using the laser scanned photodiode technique. Results show that band gap engineering together with the laser scanned photodiode technique allows a voltage controlled shift of the collection regions, allowing color discrimination at readout voltage that cancels the self-bias effect induced by the steady state illumination, across the back diode. The threshold voltage between green and red discrimination depends on the thickness ratio between a-Si:H (-i')/a-SiCH (-i) layers. As this ratio increases the self-reverse effect due to the front absorption will be balanced by the decrease of the self-forward effect due to the back absorption shifting the threshold voltage to lower reverse bias. The various design parameters and the optical readout process trade-offs are discussed and supported by a 2D numerical simulation. A self-bias model is proposed to explain the voltage controlled spectral sensitivity.

A promising candidate to etch silicon totally selective against the dielectrics is here studied. This paper reports a detailed study of the silicon chemical vapor etch with HCl/H2 mixtures. Kinetics measurements on (001)-oriented wafers permitted us to extract apparent activation energies varying from 95.2kcal/mol and 73.9kcal/mol, depending on the HCl dilution in the chamber. On the other hand, etch rates measurements as a function of the HCl partial pressure are found to follow a sub-linear behavior indicating complex mechanisms occurring with the use of the HCl/H2 gas mix. In a second part, thanks to SEM cross-section observations, morphological analysis permitted us to point out that the {311} facet behave differently as compared to the {111} and {100} planes. To conclude, we extracted rugosity data after HCl treatment from AFM measurements and all these results permitted us to validate the potential industrialization of this etching process for the formation of localized cavities or junctions on patterned wafers.

Light-weight, large-area and flexible solar cells and modules were developed. Roll-to-roll processes including an improved film deposition process named “Stepping-roll process” are used to fabricate large-area hydrogenated amorphous silicon-based solar cells in succession on plastic film substrates. A unique device having through-hole contacts was developed and applied to simplify the production processes and to generate high voltage using connection in series. Production technologies, such as (1) light-weight and large area module fabrication, (2) plasma condition controlled chemical vapor deposition, (3) low substrate temperature selective reactive sputtering, and (4) large-area uniform transparent conductive oxide film deposition are reviewed.

Epitaxial silicon thin film growth has been achieved on crystalline silicon substrates using aluminum induced crystallization of amorphous silicon. The phenomenon of layer inversion has been utilized in this process. Silicon wafers <100> were used as the starting crystalline structure for the grown films. After the wafer is cleaned a thin layer of aluminum (300 nm) was deposited by sputtering. This deposition was followed by 300 nm film of amorphous silicon deposited using plasma enhanced chemical vapor deposition method. After annealing the samples for 40 minutes at 525 °C, a continuous film of silicon was formed on the silicon substrate. X-ray diffraction spectrum indicated that this film has the same orientation as that of the substrate. Scanning electron microscopy cross section images showed indistinguishable interface between the substrate and the crystallized film. Cross sectional transmission electron microscopy studies of the crystallized structure showed epitaxial nature of the films.

Organic light emitting diode (OLED) displays are a serious competitor to liquid crystal displays in view of their superior picture quality, higher contrast, faster on/off response, thinner profile, and high power efficiency. For large area and/or high-resolution applications, an active matrix OLED (AMOLED) addressing scheme is vital. The active matrix backplane can be made with amorphous silicon (a-Si), polysilicon, or organic technology, all of which suffer from threshold voltage shift and/or mismatch problems, causing temporal or spatial variations in the OLED brightness. In addition, the efficiency of the OLED itself degrades over time. Despite these shortcomings, there has been considerable progress in development of AMOLED displays using circuit solutions engineered to provide stable and uniform brightness. Indeed the design of AMOLED pixel circuits, particularly in low-mobility TFT technologies such as a-Si, is challenging due to the stringent requirements of timing, current matching, and low voltage operation. While circuit solutions are necessary, they are not sufficient. Process improvements to enhance TFT performance are becoming inevitable. This paper will review pertinent material requirements of AMOLED backplanes along with design considerations that address pixel architecture, contact resistance, and more importantly, the threshold voltage stability and associated gate overdrive voltage. In particular, we address the question of whether conventional PECVD can be deployed for high mobility and high stability TFTs, and if micro-/nano-crystalline silicon could provide the solution.

A considerable cost reduction could be achieved in photovoltaics if efficient solar cells could be made from thin polycrystalline-silicon (pc-Si) layers. Aluminum-induced crystallization (AIC) of amorphous silicon followed by epitaxial thickening is an effective way to obtain large-grained pc-Si layers with excellent properties for solar cells. To obtain efficient solar cells, the electronic quality of the pc-Si material obtained by AIC has to be optimized and the cell design has to be adapted to the material. In this paper, we report on pc-Si solar cells made by AIC in combination with thermal CVD on ceramic alumina substrates. We made pc-Si solar cells on alumina substrates that showed Voc values up to 533 mV and efficiencies up to 5.9%. This is the highest efficiency ever achieved with pc-Si solar cells on ceramic substrates where no (re)melting of silicon was used. We demonstrate that the quality of the pc-Si material can be improved drastically by reducing the substrate roughness using spin-on oxides. We further show that a-Si/c-Si heterojunctions lead to much higher Voc values than diffused homojunctions. A cell concept that incorporates spin-on oxides and heterojunction emitters is therefore best suited to obtain efficient pc-Si solar cells on alumina substrates.

In this work we present results of studies performed on Schottky and MIS (metal-insulator – semiconductor) PSD (position sensitive detectors) structures: substrate (glass)/ Cr (300 nm) / a-Si:H [n] (37 nm) / a-Si:H [i] (600 nm) / SiO2 (1.5 nm – for the MIS) / Au (7 nm). The effect of the interfacial oxide layer between Au and a-Si:H, for the MIS structures, was studied and compared with the Schottky, in order to determine how beneficial it could be for device performances and time degradation. For doing so, the Au thickness of 70Å was deposited by thermal evaporation on an oxide free (Schottky) and oxidized (20Å) (MIS) a-Si:H surfaces. These structures were characterized by SIMS, RBS, SEM and AFM in order to correlate the obtained diffusion profile of Au at the interface and the topography with the presence of the oxide at the interface. The results show that the Au inter-diffuses very easily in the oxide free a-Si:H surface, even at room temperature, degrading the devices performance. On the other hand, the MIS structures, with their interfacial oxide present no structural changes after annealing and the PSD produced are stable. We believe that this effect is associated with the barrier effect of the interfacial oxide that prevents the Au diffusion. The optimized 1D MIS sensors are stable and exhibit a linearity error as low as 0.8 % and sensitivities of 33 mV/cm for a 5 mW spot beam intensity at a wavelength of 532 nm, while the Schottky sensors showed a time degradation of their characteristics.

We report on a systematical study of growth rate, surface morphology, hydrogen and oxygen incorporation, optical and electrical properties in Ge:H and GeYSi1-Y:H, Y> 0.85 films, deposited in a capacitive reactor by low frequency PE CVD. Silane and germane were used as feed gases diluted by hydrogen. Hydrogen dilution characterized by R= QH2/[QSiH4+QGeH4], where QH2, QSiH4, and QGeH4 are gas flows of hydrogen, silane and germane, respectively. The flow was varied in the range of R=20 to 80. Composition of the films was characterized by SIMS profiling. We did not observed a significant change of the deposition rate Vd in GeYSi1-Y:H films in all the range of R, while for Ge:H films Vd was significantly reduced after R=50. AFM characterization of the surface morphology demonstrated that at R=50 average height <H>(R) reached maximum in both Ge:H and GeYSi1-Y:H films, while average diameter <D>(R) had a minimum in GeYSi1-Y:H films and maximum in Ge:H films. Both Ge:H and GeYSi1-Y:H films demonstrated change of E04 in the studied range of R, and a minimum clearly appeared in E at R=50-60 suggesting significant reduction in weak bonds of these films. The activation energy of conductivity Ea slightly increases with R in Ge:H films and shows no definitive trend in GeYSi1-Y:H: films. Both FTIR and SIMS data show a general trend of reducing hydrogen and oxygen content with R. These two types of films showed different behavior and correlations between surface morphology and optical and electrical properties.

In this work, we investigate the influences of source gas supply method and dc substrate bias on the deposition rate as well as structural properties of μc-Si films and demonstrate the high rate synthesis of highly crystallized μc-Si films with improved film density by using a high-density and low-temperature microwave plasma source. A high flux of SiH3 and atomic hydrogen on film growing surface achieved through adjusting SiH4 gas supply configuration is effective for the fast deposition of highly crystallized μc-Si films and for the improvement of film mass density. Appropriate ion bombardment under moderate negative dc substrate bias along with the suppression of contributions of detrimental species to film growth also account for the improvement in properties of resulting films. As a consequence, a very fast deposition rate of ~65 Å/s was achieved with a high Raman crystallinity Ic/Ia>3 and a low defect density of (1-2)×1016 cm-3 despite a high silane concentration of 67%.

The effect of ambient conditions on light soaking (LS) in porous silicon (PS) sample is studied. In vacuum LS on porous silicon increases dark current (DC) while in presence of water vapor it decreases DC. Interestingly, LS gives a higher DC in vacuum as well as in presence of water vapor for boron doped hydrogenated amorphous silicon a-Si:H(B) samples. A thin layer of polystyrene polymer almost eliminates the light induced degradation of porous silicon (PS) layers but can do so only to a smaller extent in a-Si:H(B). This shows that the effect of LS in PS is different than the effect of LS in a-Si:H(B) and that the surface plays a more important role in PS than in a-Si:H.

Intrinsic hydrogenated amorphous silicon films were deposited by the DC saddle field system on crystalline silicon wafers. The substrate temperature of the amorphous film, crystalline silicon surface cleaning schemes, and the native oxide etchant were varied. The transport parameters of the amorphous-crystalline silicon heterostructures were evaluated by Photocarrier Radiometric (PCR) lifetime measurements. PCR bulk lifetime estimates were obtained using the quinhydrone in methanol solution to passivate the crystalline silicon surface. We present the effectiveness of the PCR system in evaluating different surface passivation schemes.