Refractory-metal silicides are currently receiving widespread attention because of their usefulness as interconnects in VLSI devices. Potentially the most important of these silicides is TiSi2. TiSi2 offers a sharp stable interface, a high process-compatible eutectic temperature, and the lowest resistivity of all refractory-metal silicides. Much of the previous work on TiSi2 [1-8] has been directed towards the understanding of the kinetics of silicide formation in order to optimize these electrical and interfacial properties. One parameter that may affect the silicide formation is substrate orientation [9]. We have compared the kinetics of formation of TiSi2 for Ti deposited onto p-type 10Ω-cm Si(100) and Si(111). All process parameters except substrate orientation were identical. 2800Å of Ti was electron-beam evaporated at a rate of 20Å/s and a background pressure of 9×10−8 torr onto chemically cleaned (HNO3, HF, rinse) Si substrates and subsequently annealed at temperatures between 470°C and 700°C in evacuated sealed quartz tubes. A turbopumped vacuum system was used to evacuate the quartz tube before sealing. A Ti getter was independently heated to remove remaining background contaminants prior to annealing.

Deep level transient spectroscopy (DLTS) in conjunction with other analytical techniques was used to establish a correlation between the leakage current in the TiSi2/p+/n-Si shallow diodes (0.25 micron) and the Ti-related Ec - 0.23 eV deep trap. It was found that Ti diffused into the junction region durin the TiSi2 formation and caused leakage currents with values up to 2 × 10−8 A/cm2. Further increases of the leakage current were related to the formation of a TiSi2/n-Si Schottky barrier.

A molybdenum and chromium double layer contact has been developed for the first level metallization of VLSI circuits. An 800Å layer of chromium deposited under a thick molybdenum conductor provides good ohmic contact to p+ and n+ silicon and also promotes metal adhesion to the substrate. The molybdenum has good step coverage and acceptable current carrying capacity when its thickness exceeds 5000Å. Both metals are sequentially sputtered in one pumpdown and patterned with a single RIE step using CCI4 + O2. One pm diameter contacts and 1.5µm wide lines are formed in VLSI geometries using all dry etch processes. Electrical characteristics and thermal reliability were evaluated as a function of annealing temperature. Contact resistance and shallow device junctions are stable up to 500°C for p+/n diodes and up to 450°C for n+/p diodes. The sheet resistance of the film in contact with silicon rapidly increases at 525°C as silicon outdiffuses to form (Mox Crr−x)Si2 The mechanism and cause of the high temperature degradation was studied by mean of SIMS, x-ray diffraction analysis, SEM and electrical measurements.

The electrical and microstructural changes of initially amorphous Cr75Si25 thin coevaporated alloy films have been studied as a function of temperature from room temperature to 950°C. Crystallization occurs in two stages. In the “primary” stage the major portion of the amorphous film crystallizes and a steep drop in resistivity occurs. In the “secondary” stage the amorphous residue crystallizes and is accompanied by a further gradual decrease in resistivity. The resistivity depends linearly on the volume fraction Vτ(t) crystallized to give Cr3Si only for Vτ(t) < 0.35.

Al was evaporated at oxygen partial pressures, PO2, varying between 10−7 and 10−4 Pa on substrates of silicon nitride. The substrate temperature was varied between 20 °C and 250°C. The films were annealed at temperatures up to 500°C.

For Al films deposited at 20°C, it was found that the average grain size decreases with increasing oxygen partial pressure. After annealing recrystallization was observed. The relative increase of grain size was less for higher values of pO2. Annealing gave rise to a broad grain size distribution.

For Al films deposited at 250°C, the presence of oxygen caused the growth of rough inhomogeneous films. This inhomogeneous structure remained during annealing.

Thin films of titanium borides, deposited onto silicon substrates at 600 °C using plasma enhanced chemical vapor deposition, were annealed in a furnace at temperatures from 700 °(C to 990 °C. Structural properties and electronic properties were measured for the annealed films and the asdeposited films for comparison. Sheet resistances for the films show about a 35% decrease after anneals at 990 °(C. The reduction in sheet resistance appears to be relatively insensitive to the length of the anneal time. X-ray diffraction spectra of the as-deposited films show no peaks that are attributable to crystalline titanium borides; however, there are diffraction peaks that are believed to be caused by products from reactions between the titanium borides and the silicon substrate during deposition. There is evidence that crystalline titanium diboride may start to form during the anneal at 990 °C.

This paper presents an improved new method for studying the dynamics of laser induced phase transitions down to the submicron-nanosecond scale by means of a modified commercial Transmission Electron Microscope (TEM) /1/. Results on Pulsed Laser Annealing (PLA) of amorphous Germanium and a-Si/Al films are described. Potential applications and limits of this method are briefly discussed.

We have investigated reactively sputter',d ZrN, the most thermally stable of the refractory metal nitrides, for its applicability as a submicron gate electrode. One would require for such gate electrode in addition to the lowest possible resistivity, a metal work function that will tailor the threshold voltage of metal/oxide/semiconductor (MOS) field effect transistor in such a way as to minimize the channel implant. Having these requirements in mind, we have measured the temperature dependence of resistivity, its dependence on the annealing temperature and work function of ZrN films. Our best films have resistivity, p of 20 A2-cm, comparable to TiSi. We find that p of as-deposited films being nearly stoichiometric, decreases about 20% after 1000°C anneal. Such anneal does not significantly alter the average grain size, which remains about 300 A even at this temperature. The temperature dependence of p at low temperatures indicates phonon scattering mechanism and we suggest that small amounts of oxygen are re- sponsible for residual resistance. The films undergo superconducting transition at 7.5-8 K and this transition provides an additional check on the compositonal homogeneity of the films. The work function, determined from the capacitance-voltage (C-V) characteristics of ZrN capacitors with various thicknesses of Si02, has value 0. = 4.6 Volts, at the midgap between n+ and p+ polysilicon and thus is applicable to 0.5 1m N-MOS and submicron C-MOS.

A computer model based on the finite element method has been applied to evaluate the effect of the parasitic area between contact and diffusion edges on end resistance measurements in four terminal Kelvin resistor structures. The model is then applied to Al/Ti/n+ Si contacts and a value of contact resistivity of Qc = 1.8×10−7.Ωcm2 is derived. For comparison, the use of a self-aligned structure to avoid parasitic effects is presented and the first experimental results obtained on Al/Ti/n+Si and Al/CoSi2/n+Si contacts are shown and discussed.

Data is presented which links the 620 - 660 cm−1 infrared absorption doublet in porous silicon films to the presence of silicon hydride. This band assignment explains both the magnitude and thermal behavior of the doublet, and is in agreement with published data on silicon hydrides.

Phosphorus segregation at grain boundaries in thin film polycrystalline silicon has been investigated by nuclear magnetic resonance spectroscopy. Amorphous silicon thin frims were deposited by plasma enhanced chemical vapor deposition with 1% phosphine in silane. The films were subsequently annealed at 700°C and 800°C to produce a fine grained polycrystalline material. All of the phosphorus atoms were found to be four-fold coordinated at the grain boundary. The P atoms were found to have three different environments in the grain boundary region. These results will be discussed in relationship to the carrier trapping and dopant segregation models.

A novel technique for the fabrication of shallow, silicided p+-n junctions with excellent electrical characteristics has been developed. The technique utilizes the ion implantation of dopants into silicide layers formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of implanted dopants into the Si substrates to form shallow junctions. This technique can be easily applied to the fabrication of MOSFETs in a self-aligned fashion, and can have a significant impact on CMOS VLSI technology.

Highly selective metal and alloy deposition with simultaneous silicide formation - on semiconductor substrates immersed in commercial electroplating solutions has been investigated via pulse laser irradiation without masking procedures and external electric current.

Specimens of 5i and GaAs substrates, immersed in gold and in palladiumnickel electroplating solutions, were irradiated by a Qswitch YAG pulse laser perpendicular to their surfaces at predesired local zones. The gold, palladium and nickel deposits thus obtained were subsequently examined and characterised by SEM, TEM, AES, ESCA and RBS.

Deposit thickness ranged from a few hundred angstroms to several micrometers, depending primarily on the laser irradiation energy. The elemental Gold deposit exhibited Schottky barrier contacts with the GaAs and Si substrates. Palladium and nickel silicides obtained on n-type silicon substrates likewise exhibited Schottky behavior contracts.

Stresses in WSi2 films prepared by chemical vapor deposition have been examined using an optically levered laser beam during typical processing cycles to 900 C. Initial heating produces tensile stress levels of 1.0 GPa at 500 C with crystallization into the inetastable hexagonal form. Cooling from this temperature results in room temperature stresses of 1.2 GPa. A large decrease in the tensile stress level accompanies the transformation into the stable tetragonal structure during heating from 500 C to 750 C. Films in this form are mechanically stable and respond elastically to further thermal cycling.

Films of TaSi2 sputtered from an intermetallic target and co-sputtered from elemental targets have also been investigated. Initial heating of films sputtered from the intermetallic target produces a tensile stress state during crystallization which is high but slightly less than observed during crystallization of WSi2. This high tensile state is not observed in films deposited in layers from elemental targets. The appearance of a metastable phase is not observed for intermediate anneals in either case. The initial crystallization results in the stable phase of hexagonal TaSi2. Fully annealed films are elastic below 920 C.

Rapid Thermal Processing (RTP) can minimize processing time and therefore minimize dopant motion during annealing of ion implanted junctions. In spite of the advantage of short time annealing using RTP, the formation of shallow B junctions is thwarted by channeling, transient enhanced diffusion and concentration enhanced diffusion effects all of which lead to deeper B profiles. Channeling and transient enhanced diffusion can be avoided by preamorphizing the silicon before the B implant. However, defects at the original amorphous/crystal boundary persist after annealing. Very low energy B implantation can lead to very shallow dopant profiles and in spite of channeling effects, offers an attractive potential shallow junction technology. In all of the shallow junction formation techniques RTP is required to achieve both high activation of the implanted species and minimal diffusion of the implanted dopant.

As a result of device scaling very shallow low resistance diffusions are required for VLSI CMOS fabrication. This paper describes a technique for their formation using silicon implantation for preamorphisation, counterdoping arsenic implantation and overall boron fluoride implantation for the sources and drains of the n- and p-channel transistors. Platinum silicidation has been used to reduce diffusion and polysilicon sheet resistances to 8Q/square. Activation of the shallow diffusions has been achieved either by furnace annealing (FA) or rapid thermal annealing (RTA) in the range 900°C to 1100 °C. Materials results are discussed including TTEM, SIMS and SR profiling. The suitability of the technique for VLSI CMOS applications is demonstrated by the fabrication of sub-micron transistors. With larger wafer diameters (>5') the FA conditions considered are not practicable owing to ramped diffusion effects which lead to deeper junctions. Hence RTA is necessary: optimum conditions found were 1100 °C for 10 seconds when device performance equivalent to or better than FA can be achieved.

The diffusion of ion-implanted dopants in silicon during rapid thermal annealing is modeled using the finite difference method.The change in impurity profile for an initial Pearson IV boron implant is negligible(less than 1 % change in junction depth) when the peak annealing temperature(TP ) is less than 1050 °C and its duration is shorter than 20 seconds. The dopant redistribution becomes significant(greater than 25 % change in junction depth) when Tp is greater than 1200 °C and its duration is longer than 40 seconds.The heatup and cooldown portions of the transient annealing cycle are found to have little effect on dopant redistribution provided that their rates are higher than 120 °C per second.

Rapid thermal annealing of arsenic and boron difluoride implants, such as those used for source/drain regions in CMOS, has been carried out using a scanning electron beam annealer, as part of a study of transient diffusion effects. Three types of e-beam anneal have been performed, with peak temperatures in the range 900-1200°C; the normal isothermal e-beam anneals, together with sub-second fast anneals and ‘dual-pulse’ anneals, in which the sample undergoes an isothermal pre-anneal followed by rapid heating to the required anneal temperature in less than O.5s.

The diffusion occuring during these anneal cycles has been modelled using SPS−1D, an implant and diffusion modelling program developed by one of the authors. This has been modified to incorporate simulated temperature vs. time cycles for the anneals. Results are presented applying the usual equilibrium clustering model, a transient point-defect enhancement to the diffusivity proposed recently by Fair and a new dynamic clustering model for arsenic. Good agreement with SIMS measurements is obtained using the dynamic clustering model, without recourse to a transient defect model.

Defects remaining in diodes fabricated with the forementioned implants after these anneal cycles have been studied using DLTS techniques. Trap densities for the three types of e-beam anneal are comparable to those for furnace annealed diodes, as are the reverse leakage currents measured (typically 2–5nA for a 0.85mm2 diode at -5V).

Mo-gate n-channel poly-Si TFTs have been fabricated for the first time at a low processing temperature of 26°C. 500 to 1000A thick a-Si:H was successfully crystallized by pulsed XeCl excimer laser (308nm) annealing without heating the glass substrate. The channel mobility of the TFT was 180 cm2/V.sec when the a-Si:H was annealed at energy density of 200 mJ/cm2.

This paper summarizes the development in the direction of rapid isothermal processing (RIP) dominated silicon integrated circuit fabrication technology.