We discuss the applicability of ultrathin SiO2 layers as a mask for low-temperature selective-area deposition of Si. Thin oxide layers with estimated thickness ranging from 4 to 20 Å were formed by oxidizing H-terminated Si(100) surfaces by a remote plasma exposure at room temperature. Low-temperature selective-area deposition was carried out using two different techniques: flow-modulated plasma-enhanced chemical vapor deposition (FM-PECVD) using SiH4 and H2, and very low pressure CVD (VLPCVD) using Si2H4. We show that the ultra-thin plasma oxide layers exhibit good properties for a use as a passivating mask layer, and that the oxide layer can be patterned directly by E-beam irradiation. These results open up a possibility to realize Si-nanostructures formation by selective-area processing. Degradation of the oxide layer by plasma processing is also discussed.

A novel method for the fabrication of poly-Si films with a large grain size is reported using solid phase crystallization (SPC) of LPCVD amorphous Si films by nucleation interface control. The reference films used in this study were 1000 Ǻ -thick a-Si films deposited at 500°C at a total pressure of 0.35 Torr using Si2H6/He. Since the deposition condition changes the incubation time, i.e. nucleation rate, and since nucleation occurs dominantly at a-Si/SiO2 interface, we devised the following deposition techniques for the first time in order to obtain the larger gain size. A very thin a-Si layer (~ 50 Ǻ) with the deposition conditions having long incubation time is grown first and then the reference films (~ 950 Ǻ) are grown successively. Various composite films with different combinations were tested. The crystallization kinetics of composite films was observed to be determined by the deposition conditions of a thin a-Si layer at the a-Si/SiO2 interface. Nucleation interface was also observed to be modified by interrupted gas supply resulting in the enhancement of the grain size.

Three important oxidation regimes have been identified in the temporal evolution of the wet thermal oxidation of AlxGa1-xAs (1 ≥ x ≥ 0.90) on GaAs: 1) oxidation of Al and Ga in the AlxGa1-xAs alloy to form an amorphous oxide layer, 2) oxidative formation and elimination of elemental As (both crystalline and amorphous) and of amorphous As2O3, and 3) crystallization of the oxide film. Residual As can result in up to a 100-fold increase in leakage current and a 30% increase in the dielectric constant and produce strong Fermi-level pinning and high leakage currents at the oxidized AlxGa1-xAs/GaAs interface. The presence of thermodynamically-favored interfacial As may impose a fundamental limitation on the application of AlGaAs wet oxidation for achieving MIS devices in the GaAs material system.

The oxidation of high Al content AlxGa1-xAs has received much attention due to its use in oxide-aperture, vertical-cavity surface emitting lasers (VCSELs) and for passivating AlAs against environmental degradation. We have recently identified the spinel, gamma phase of Al2O3 in layers laterally oxidized in steam at 450°C for =0.98 & 0.92 and have seen evidence for an amorphous precursor to the gamma phase. At the interface with the unoxidized AlxGa1-xAs , an ~17nm amorphous phase remains which could account for the excellent electrical properties of oxide-confined VCSELs and help reduce stress concentrations at the oxide terminus.

The surface structure of Si(111) post-annealed at 980 °C after nitrogen ion induced nitridation has been investigated by using a scanning tunneling microscope (STM) and low energy electron diffraction (LEED). The LEED and STM results indicated the formation of ordered domain of quadruplet structure in the silicon nitride layer. The LEED pattern taken from the nitrated Si(111) surface showed a coexistence of 7×7 domain with quadruplet one. In the STM image taken from the same surface, a three directional periodicity with a periodic arrangement of white protrusions was observed in the local area of silicon nitride island and its symmetry directions were rotated about 10° with respect to those of Si(111) surface. In addition to the quadruplet structure of the silicon nitride island, meta-stable structures such as 9×9, c(4×2), and 2×2 as well as 7×7 phase boundaries were observed to have been formed on the Si(111) surface during the rapid cooling of nitrated surface from the post-annealing temperature of 980 °C. The investigation of the surface structure of nitrated Si(111) showed that the surface nitrated at high temperature had better epitaxial silicon nitride layer than that post-annealed after nitridation at room temperature.

A transmission electron microscope technique is used to image atomic steps at buried interfaces between silicon and silicon dioxide. We have studied the effect of processing conditions on the interfacial structure of Si/SiO2 with this technique. We observed a dramatic effect of post-oxidation annealing on silicon (100). Roughening of Si(111) interfaces due to chemical preparation is also reported.

Thin films of anatase TiO2 have been deposited on tin-doped indium oxide (ITO) and Sb-doped tin oxide using electron beam evaporation. Subsequently these samples have been mounted into an electrochemical cell. Assuming a composition of LixTiO2 with x being 0.5 or 1, voltammetric measurements show that all lithium is present within the first 15 or 7.5 nm of the TiO2 film, respectively. Stepped potential experiments in combination with optical transmission measurements show that de-intercalation is much faster than intercalation. Differential absorption spectra as a function of intercalation potential suggest that the observed dark coloring of intercalated anatase can be attributed to electron traps at Li+ sites. This contradicts assumptions made in literature that the coloring mechanism of anatase is based on intervalence charge transfer from Ti4+ to Ti3+.

The low temperature oxidation is effective for the atomically-controlled gate oxide growth. We focused the effects of post-oxidation annealing (POA) and attempted to improve the properties of the low-temperature-grown ultrathin oxides with a thickness of 3nm by POA. POA abruptly reduced the leakage current at a low gate voltage below 1.5V and the interface trap density. The correlation between the interface trap and the leakage current at a low applied voltage region were confirmed. We found that the stressing immunity of the ultrathin oxides grown at a low temperature, 650°C, is drastically improved by POA at 850°C.

Suitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and capacitance-voltage measurements were done on 190Å layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide. Measurements of the high and low frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

We present characteristics of Al/Si3N4/Si/n-GaAs metal-insulator-semiconductor (MIS) interfaces grown on GaAs(111)B prepared with a combination of in situ molecular beam epitaxy (MBE) and chemical vapor deposition (CVD) techniques . The density of the surface states in the high 1010 eV-1 cm-2 near the GaAs midgap for the GaAs grown at 575°C and 625°C was obtained. The MIS structure with GaAs homoepitaxial layer grown at 625°C, showing smoother surface morphology than the surface grown at 575 °C, exhibited small hysteresis which was as small as 30 mV under a field excursion of 1.5 MV/cm. The presence of a 1 MHz frequency response at 77 K suggests that the traps be within 60 meV of the conduction band edge of GaAs.

An interfacial layer is formed between the TEOS(tetraethylorthosilicate) based oxide and silicon substrate when the oxide is thermally treated and it shows unique properties by leaving a unremovable layer in an H F(hydrofluoric acid) dipping. While the interface formed in the temperature range of 950 - 1100 °C demonstrates hydrophilic state, it renders the surface hydrophobic in the higher range of 1150 - 1200 °C. Its characteristics are analyzed by ESCA and the measurement of water contact angle on the silicon surface after stripping the oxide.

The influence of interfacial nanostructure on electron emission from diamond coated Mo emitters is presented. Diamond coating is known to increase electron emissivity, but interfacial oxides and an amorphous layer change the magnitude. After annealing, emissivity was enhanced further and Mo2C was formed at the interface, as well as a decrease in the oxides and amorphous layers. The shape of the FEM image changed but no individual emitting sites were observed. Possible mechanisms causing these changes are discussed.

A novel technique to realize a selectively grown Si epitaxy layer has been developed. This technique consists of deposition of amorphous Si with oxide-free Si surface, selective solid phase epitaxial (SPE) growth on Si windows, and etching of uncrystallized amorphous Si on SiO2 layer. Formation of surface oxide can be effectively suppressed by flowing Si2H6 gas during heating-up stage to the deposition temperature. This method enables us to grow epitaxial layer without any high temperature cleaning procedures. Substantially higher growth rate of vertical SPE on Si windows over lateral SPE on SiO2 regions allows the growth of thick SPE layer with a minimized lateral overgrowth. With a proper etching solution, the remaining amorphous Si on SiO2 layer can be readily etched to form a selectively defined epitaxial layer on Si windows.

The growth of high quality Te on misoriented Si(100) is important as an intermediate phase for epitaxial growth of CdTe. The misorientation angle plays a key role in the growth quality of CdTe/Si(100); this incited our curiosity to investigate the effect of the misorientation angle on the topography of the surface structure of Si(100). Our main goal is to show the relation between the misorientation angle, the terrace width and the step height distributions. HRLEED ( High Resolution Low Energy Electron Diffraction ) provides information in reciprocal space while STM gives real space topographic images of the surface structure. STM and HRLEED measurements were performed on Si(100) with misorientation angle υ= 0.5°, 1.5° and 8° towards the ]110] direction and υ= 4° towards the ]130] direction. Except for the 8° misorientation in which case a regular step array with diatomic step height was observed, for the other misorientations the terrace width was variable. The average terrace width decreased with increasing misorientation angle. A mixture of diatomic and monatomic step heights was observed on the 0.5° and 1.5° misoriented Si(100) samples. It proves that one can not assume purely monatomic step height for low misorientation angles. Our results do not agree with the belief that at low miscut angle A and B terraces are equal and that as the misorientation angle increases the B terrace tends to be wider than the A terrace. In fact, pairing of terraces was not observed at all. Te was deposited at a substrate temperature of 200 C. We observed a significant reduction in the terrace widths for all miscut angles.

Transmission electron microscopy is used to investigate the structural development as a function of the annealing temperature of Co-silicides prepared on SiGe and SiGeC. The transition temperature from Co(SiGe) into Co(SiGe)2 is higher for SiGeC than for SiGe.

Cobalt disilicide films have been formed on strained epitaxial Si0.80Ge0.20/Si(100) alloys via co-deposition of silicon and cobalt. Co-deposition is shown to improve the epitaxy and prevent the phase segregation commonly observed with the formation of Co/SiGe contacts using other methods such as the direct deposition of cobalt onto SiGe or the sequential deposition of a silicon sacrificial layer and cobalt onto SiGe. EXAFS measurements at the cobalt K edge indicate that co-deposited films annealed at 500–700° C are indeed crystalline CoSi2 throughout this temperature range. The XRD patterns of the co-deposited films do not exhibit any of the CoSi2 (111), (220) or (311) peaks normally associated with other preparation methods. The sheet resistance and r.m.s. roughness of the CoSi2 films increase monotonically with annealing temperature. These results indicate that co-deposited films are epitaxial to the (100)-oriented SiGe substrate and suggest that low thermal budget, low resistivity contacts to strained SiGe can be grown with this method. Issues related to the presence of Ge at the CoSi2/substrate interface will be discussed.

The energetics of copper segregation to silicon surfaces were examined by measuring the Cu coverage after equilibration between Cu on the surface and internal Cu3Si, for which the Cu chemical potential is known. For oxide-free surfaces the Cu coverage was close to one monolayer on (111) surfaces but was much smaller on (100) surfaces. The Cu coverage was greatly reduced by oxide passivation of the surface. LEED showed the 7×7 structure of the clean (111) silicon surface converted to a quasiperiodic 5×5 structure after equilibrating with Cu3Si. The 2×1 LEED patterns for (100) surfaces indicated no change in surface structure due to the Cu3Si. These results show that the free energy of copper in Cu3Si is higher than that of copper on (111) surfaces but lower than that of copper on (100) surfaces.

A soft X-ray emission spectroscopy(SXES) study under an energetic electron irradiation has been applied to a nondestructive buried interface analysis of a thin-film(e.g., Cr)/Si(substrate) contact system, where the energy of primary electrons, Ep , is less than 20keV. An interesting point of this method is that we can have a specific signal for an element to be used as a finger print, otherwise it is difficult. By using this e-beam excited SXES, we can study an interface buried deep in a rather thick overlayer, e.g., more than a hundred of nm, which is due to the fact that a mean free path of a soft X-ray or an X-ray production depth is much larger than the mean free path of an energetic electron in solids. Electronic structural study of silicides by SXES is also shown.

Chemistry and interfacial reactions of the Cu-Ge alloyed ohmic contacts to n-GaAs with extremely low specific contact resistivity (6.5×10-7 Ω·cm2 for n~1017 cm-3) have been investigated by transmission electron microscopy, EDX and SIMS. Unique properties of the contact layers are related to the formation (at Ge concentration above 15 at.%) of a polycrystalline layer of ordered orthorhombic ε1-Cu3Ge phase. Formation of the ε1-phase is believed to be responsible for high thermal stability, interface sharpness and uniform chemical composition. The results suggest that the formation of the ζ- and ε1,-Cu3Ge phases creates a highly Ge-doped n+-GaAs interfacial layer which provides the low contact resistivity. Layers with Ge deficiency to form ζ-phase show nonuniform intermediate layer of hexagonal β-Cu3As phase which grows epitaxially on Ga{111} planes of GaAs. In this case, released Ga diffuses out and dissolves in the alloyed layer stabilizing the ζ-phase which is formed in the structures with average Ge concentration of as low as 5 at.%. These layers also exhibit ohmic behavior.

Pt embedded ohmic contacts to n+-GaAs (AuGe-800 Å/ Ni-150 Å/Pt-200 Å/Au-500 Å and AuGe-800 Å/Pt-200 Å/Ni-150 Å/Au-500 Å/n+-GaAs) have been developed for the advanced discrete devices and MMIC (monolithic microwave integrated circuit) applications. The specific contact resistance investigated by Transmission Line Method is 1x10-6 Ω cm2. Ohmic contact reliability investigated by thermal storage test at 300 °C under N2 ambient demonstrated nearly the same contact characteristics after 3000 hours. In both systems, X-ray diffraction results and Auger depth profiles show that the good ohmic contact is related to the formation of Au7Ga2, PtAs2, and Ni19Gen12 phases. AuGa compound enhances the creation of Ga vacancies, allowing incorporation of Ge into Ga sites, and PtAs compound is piled up in the middle of AuGa layer to suppress As outdifrusion from GaAs substrate. TEM cross-sectional view indicates that metal/n+-GaAs reaction layer is ∼ 1200 Å beneath GaAs. Surface and interface are very smooth and abrupt in comparison to conventional AuGe/Ni/Au contact.