The ion implantation of germanium into 4H-SiC at 1000 °C resulted in crystalline SiC:Ge layers that are coherently strained to the (0001) oriented 4H-SiC substrates. Germanium implantation energies of 140 keV and 50 keV were chosen to form approximately 100nm thick step-like SiC:Ge layers with Ge atomic fractions ranging from 0.0007 to 0.006. High-resolution x-ray diffraction (HRXRD) and reciprocal space mapping reveal a high-quality, compressively strained SiC:Ge layer. High-temperature annealing resulted in partial relaxation of the macroscopic layer strain, however the SiC:Ge layer remained strained with a coherent interface for annealing up to at least 1650°C. Because Ge is a group-IV atom like Si and C, its incorporation into the lattice is expected to act as an isoelectronic impurity, rather than a charged donor or acceptor. Thus, high-quality, SiC:Ge layers have the potential for bandgap and strain engineered electronics such as SiC-based high electron mobility transistors (HEMTs) for RF-power electronics. Currently there is no established heterojunction pair in SiC material technology for fabricating HEMTs and other heterojunction devices.

Metal-semiconductor-metal (MSM) memory devices have been made in hydrogenated amorphous silicon carbide (a-SiCx:H). Switching in silicon-rich amorphous silicon alloys is believed to be related to the concentration of defects in the semiconductor material. We have used ion bombardment to introduce a controlled number of damage centres into amorphous silicon carbide. Both analog and digital switching behaviours are reported.

Three possible situations of extended defect formation during sublimation growth of SiC have been investigated: a-plane growth, occurrence and effect of irregular growth interfaces, and development of elongated open volume morphological defects. While in the first case the most preferred defects are basal plane stacking faults (SFs), in other studied samples threading dislocations and high energy SFs have been revealed, these suggesting stress accumulated in the course of the growth process. Formation of morphological defects of the above character has been observed in the presence of micropipes and step flow growth mode on vicinal surfaces. Growth on atomically flat surfaces can eliminate this type of defects but the polytype uniformity is more difficult to maintain.

Atomistic structures of amorphous silicon carbide generated by energetic particles were examined by electron diffraction techniques in combination with imaging plates. Atomic pair distribution functions revealed that not only heteronuclear (silicon-carbon) bonds but also homonuclear (silicon-silicon and carbon-carbon) bonds exist in the first coordination shell of amorphous silicon carbide induced by ion- or electron-beam-irradiation. Structural changes from amorphous silicon carbide to amorphous silicon were observed under the electron irradiation.

High-resolution X-ray diffraction (HRXRD) combined with other diffraction techniques is applied to characterize 3C SiC epilayers hoteroepitaxially grown on atomically flat mesas on 4H and 6H SiC substrates. Small-beam rocking curve scan and reciprocal mapping show extremely high crystalline perfection and homogeneity of the ideally grown 3C-SiC epilayers. Accurate lattice measurements based on X-ray multiple-order reflections reveal that: 1) no misorientation between the (0001) lattice planes across the 4H/3C or 6H/3C interface is detected, confirming the 2D nucleation mechanism of the 3C epilayer from a flat coherent interface; 2) in-plane substrate/epilayer lattice mismatch always exists, but the 3C epilayers do not correspond to a completely relaxed cubic structure, indicating that the epilayers are partially strained; 3) lattice mismatch varies for different regions, implying a complicated strain relaxation mechanism of 3C epilayers on various mesas.

The Hall scattering factor of holes rH,h(T) in 4H- and 6H-SiC is determined by comparing the temperature-dependent free hole concentration p(1/T) obtained from Hall effect and from the neutrality equation with defect parameters, which are independently determined by SIMS and C-V measurements. rH,h(T) strongly deviates from 1 and assumes values between 1.4 and 0.5 at temperatures ranging from 100K to 800K. rH,h(T) is identical for 4H-and 6H-SiC within the measurement uncertainty. Al-doped SiC epilayers of the 3C-, 4H- and 6H-polytype were investigated with admittance spectroscopy and DLTS prior to and subsequent to processing steps. Depending on the SiC polytype, a different number of shallow acceptors is observed, which are thermally stable up to high temperatures (1700°C).

Structure and composition are reviewed for different surface phases of SiC(0001) and SiC(0001). The chemistry of well ordered phases spans from Si rich to graphitic composition with the excess elements arranged in adlayers and/or large scale reconstruction patterns. On SiC(0001) the Si rich (3×3) surface allows for step flow growth of monocrystalline homoepitaxial layers due to an extremely efficient dangling bond saturation. Si rich preparation or oxidative treatment are used for a controlled evolution of different stacking sequences on the adatom phase on SiC(0001) and could be utilized for the development of polytype heterostructures. On SiC(0001) a (2×2) phase shows three-fold coordinated adatoms with a different surface stacking reflecting the different growth behaviour of this surface. An epitaxially well matching silicon oxide monolayer can be prepared on both surface orientations by using a hydrogen etching or plasma treatment promising to facilitate low defect oxide films for MOS devices.

This paper reports initial demonstration of a cantilevered homoepitaxial growth process that places screw dislocations at predetermined lateral positions in on-axis 4H-SiC mesa epilayers. Thin cantilevers were grown extending toward the interior of hollow pre-growth mesa shapes etched into an on-axis 4H-SiC wafer, eventually completely coalescing to form roofed cavities. Each completely coalesced cavity exhibited either: 1) a screw dislocation growth spiral located exactly where final cantilever coalescence occurred, or 2) no growth spiral. The fact that growth spirals are not observed at any other position except the central coalescence point suggests that substrate screw dislocations, initially surrounded by the hollow portion of the pre-growth mesa shape, are relocated to the final coalescence point of the webbed epilayer roof. Molten potassium hydroxide etch studies revealed that properly grown webbed cantilevers exhibited no etch pits, confirming the superior crystal quality of the cantilevers.

Recently, an advanced technique for growing free-spreading SiC bulk crystals by sublimation has been demonstrated. This method was used to grow 6H- and 4H-SiC boules free of polycrystalline deposits on the crystal periphery, up to 35 mm in diameter with the micropipe density less than 20 cm-2 and the dislocation density about 102-103 cm-2. In this paper, we report on the numerical modeling of free-spreading crystal growth. We consider the global heat transfer in an inductively heated growth system, species transport in the growth cell and in the powder charge, and thermoelastic stress, focusing on the crystallization front dynamics, poly-SiC deposition, and powder source evolution. Special attention was given to the validation of the simulations. The computed thermal field and evolution of the powder and crystal shape were found to agree qualitatively with observations.

Focussing on unipolar SiC power devices a variety of applications are described, where cost reduction can be a achieved on system level even for SiC device costs being several times higher than the costs of the competing Si devices. Based on the specific properties of SiC devices like Schottky diodes and JFETs it is explained with the help of these examples how this is attainable.

The mobility of electrons in inversion layers at SiC/SiO2 interfaces μinv has been characterized in 4H- and 6H-SiC using Hall effect measurements. In order to understand the cause of the low mobilities typically observed in SiC MOS devices, a semi-empirical mobility model has been developed based on a previous model for silicon inversion layers. Using this model, two scattering mechanisms, surface phonon and Coulomb scattering from high densities of electrons trapped at the SiC/SiO2 interface, are found to account reasonably well for the behavior of the mobility. The model employs a changing density of trapped electrons as a function of gate voltage to accurately model Coulomb scattering. Surprisingly, evidence of surface roughness scattering is not observed in any SiC MOS device.

Channel-recessed 4H-SiC MESFETs were fabricated and demonstrated excellent small signal characteristics. A saturated current of 250 − 270 mA/mm at Vgs = 0 V and a maximum transconductance of 40 − 45 mS/mm were measured for channel-recessed devices with a gate length of 0.45 m. The three-terminal breakdown voltages (Vds) range from 120 V to 150 V. The Ft and Fmax of the 2 × 200 m devices were measured to be 14.5 GHz and 40 GHz, respectively. The channel recess technique results in a lower saturation current but higher breakdown voltage which makes it possible for the devices to operate at high voltages. Si3N4 passivation suppresses the instability in DC characteristics and improves CW power performance by reducing the surface effects. Less dispersion in the drain current during a power sweep was observed after passivation.

Porous 6H-SiC and 4H-SiC wafers formed by anodization have been characterized in this study prior to and following the CVD deposition of SiC epitaxial layers, using a combination of synchrotron white beam x-ray topography (SWBXT), SEM, TEM and optical microscopy. Under the high temperatures employed during epitaxial growth, a significant change in pore morphology occurs. While no evidence of reduced screw dislocation density in the epilayers is obtained, a small tilt of the epilayers with respect to the porous substrate observed on x-ray topographs could play a role in limiting penetration of defects from the substrate.

High Power asymmetric SiC GTOs (Gate Turn-Off Thyristors) were fabricated on n-type 4H-SiC substrates with multiple epi-layers and were tested to investigate breakdown voltage, maximum current density, switching characteristics, and temperature dependences.

Comparison of breakdown voltages achieved by GTOs with Guard Ring edge termination and GTOs with a proprietary Junction Termination Extension (JTE) fabricated on the same wafer are made. Individual GTOs with a nominal area of 4 mm2 (2 mm × 2 mm) utilizing the JTE were tested in forward bias and found to support over 6 kV at leakage currents of less than 5 μA. In addition, GTOs with a nominal area of 0.25 mm2 (0.5 mm × 0.5 mm) utilizing the JTE were found to support over 7 kV. These blocking voltages are the highest reported for GTOs in SiC. [1–5] Wafer maps of the breakdown voltages for older and newer wafers suggest an improvement of the material. The defect density for the newer wafer is estimated to be greater than the micropipe density.

The on-state characteristics are equally impressive, with 4 mm2 GTOs carrying > 1000 A/cm2. The GTO has a forward voltage drop of 3.66 V at a current density of 300 A/cm2 at room temperature and a forward voltage drop of 3.1 V at 300 A/cm2 at 224 °C. This indicates that on-state losses should not be excessive, even at high current densities and high temperatures.

A description is given of the profiling of CVD grown 3C SiC on undulant (001) Si using low temperature photoluminescence (LTPL). Inelastic neutron scattering (INS) and X-ray Raman scattering (XRS) are compared for acoustical modes of 4H SiC. Schottky barrier heights are obtained for 4H and 6H SiC on different crystal faces using three different measuring techniques. Scanning electron microscopy (SEM) is used to display a variety of porous SiC morphologies achieved in n-type and p-type SiC.

This paper is intended to be the introduction to the “CHARACTERIZATION” section of this volume. To serve this purpose we illustrate the subject matter with new results using four distinct experimental techniques.

Chemical vapor deposited (CVD) silicon carbide (SiC) ceramic material was joined to itself via an air stable, silver-based active brazing alloy (ABA). The microstructure and microchemistry of the interface was characterized using transmission electron microscopy (TEM), scanning electron microscopy (SEM), and electron probe microanalysis (EPMA). Results were compared to previous studies on the active alloy brazing of sintered silicon carbide using higher copper alloys.

We report on experimental studies and thermodynamic modeling of the reaction of O2 with the 4H- and 6H-SiC surfaces at high temperatures. This reaction leads to the growth of passivating SiO2 layers at high O2 pressures, etching of the surfaces at lower pressures, and enhancements of the surface segregation of carbon at still lower pressures. A pressure-temperature phase diagram for the oxidation of SiC is presented. Evidence for the thermal decomposition of the SiO2 layer on SiC is also presented.

We report on non-contact and non-destructive spatially resolved characterization of traps and luminescence centers in vanadium-free semi-insulating 6H-SiC. Two optical techniques were employed: photoluminescence (PL) mapping and thermally stimulated luminescence (TSL) imaging on SiC wafers. PL and TSL topography reveal inhomogeneity at the periphery regions of the wafers. Low-temperature PL spectra show broad bands with the maxima at 1.75eV and 1.2eV, including a sharp zero-phonon line at 1.344eV. The TSL glow curves at T>80K show different peaks in the visible and infrared bands. The luminescence spectrum of the 105K TSL peak replicates 1.75eV band, while the 120K peak corresponds to the 1.2eV band. Additionally, the high temperature TSL peak at 210K shows an excellent match with 1.344eV zero phonon line. The trap energies of different peaks are calculated. We discuss a model of complex defects composed of closely spaced electron (hole) trap and UD3 defect.

In this paper, high performance, high voltage NPN bipolar junction transistors in 4H-SiC are presented for applications in low frequency (< 5 MHz) power conversion systems as well as in RF (425 MHz) power amplifiers. The power BJTs for low frequency switching applications were designed to block 1300 V and showed a specific on-resistance of 8.0 mohm-cm2, which outperforms all SiC power switching devices ever reported. Moreover, these transistors show a positive temperature coefficient in the on-resistance and a negative temperature coefficient in the current gain, which enable easy paralleling of the devices. In addition, RF BJTs were designed, fabricated and tested for operation at UHF frequencies. The common emitter breakdown voltage was in excess of 500 V consistent with the 5 micron collector thickness. For VCC = 20 V, fT peaked at about 1.5 GHz. A single cell was measured in common emitter mode with a collector supply voltage of 80 V in class AB at 425 MHz. A 100 μs pulse width with 10% duty cycle was used. A maximum output power of 50 W for a single cell was achieved. The peak large signal power gain was 9.6 dB. The collector efficiency at the power output of 50 W was 51% with a power gain of 9.3 dB. This represents the first demonstration of a SiC RF BJT.

Amorphous silicon carbide (SiC) films were deposited on silicon substrates by thermal chemical vapor deposition (TCVD) technique, at substrate temperatures ranging from 620 °C - 850 °C. A novel, single-source halide free precursor, SP-4000, belonging to the family of polysilenemethylenes (PSM) (nominal structure [-SiH2-CH2-]n, n = 2–8 including branched and cyclic isomers) was used as source. Argon was used, as both the precursor carrier gas and the dilution gas. Other reactants, such as hydrogen or hydrocarbons, were not used. The deposition yielded films with Si/C ratio of 1±0.2. The highest achieved growth rate was 83 nm/min.

The modulus of elasticity and the nanohardness of the SiC films were measured with the aid of a nanoindenter at various depths, which did not exceed 25% of the film thickness. The average nanohardness at indentation depths of approximately 10% of the film thickness was measured up to 13 ± 4 GPa. The results of the nanoindentation will be discussed in conjunction with the microstructural analysis of the films.

In addition, the development of a viable TCVD SiC process presents significant opportunities in the nano/micro systems field. In particular, the ability to custom tailor the surfaces of microfluidic structures allows for the development of valves, pumps and channels for use in corrosive or high temperature environments. Initial results from the deposition of SiC films on prototype microfluidic components will be presented.