Electron spin resonance study of low-κ insulating layers reveals that from a defect perspective these materials resemble oxygen-rich silicon dioxide matrices. The films fabricated using chemical vapor deposition in combination with porogen technology also contain a considerable amount of residual carbon in the form of clusters. Furthermore, ion sputtering damage generates additional defects provisionally identified as dangling bonds in the silicon oxycarbide clusters. The density of these defects is found to increase with increasing porosity of the low-κ insulator. Nevertheless, a lower defect density may be attained if using a porogen-free self-assembly technology.

The continual miniaturization of microprocessors has resulted in increased RC delay and cross talk noise. To solve these problems ultralow nanoporous dielectric materials are required but have not developed yet. To develop ultralow dielectric materials with required mechanical and dielectrical properties for next generation semiconductors, it is essential to control the pore size in nm range and its morphology by preventing porogen aggregation. Thus we have used ozone treatment during thermal curing process of the nanoporous dielectrics in order to increase the reactivity between the matrix and reactive porogens and to possibly induced changes in Si bond structures.

Ozone treatment was quite effective in enhancing the reactivity of the low-k matrix and the reactive porogen, which converted effectively the alkoxy or alkyl groups into Si-OH groups, which mostly converted to the formation of Si-O-Si network structures. Therefore, ozone treatment greatly increased modulus up to 11.25 GPa at the same porogen loading (60 vol%). The modulus increased by more than 23% compared with non-treated samples (9.1 GPa). The porosity of the ozone-treated sample reduced to 19.3 vol% at the same porogen loading. Solid state Si-NMR showed that less porosity was related to the breakage of methyl groups in the matrix by ozone irradiation, which also resulted in a little sacrificed dielectric constant.

In general, the mechanical properties of nanoporous dielectrics deteriorate sharply above certain high porosity ca. 15 ~20 vol% due to non-uniform distribution of nanopores, their aggregation and resultant open pores. Therefore, this result may suggest the possibility of increasing mechanical properties of nanoporous dielectrics. However, we need to experimentally control processing variables such as irradiation time, intensity, temperature and so forth in order to optimize both mechanical and dielectrical properties.

The impact of microbump geometry, layout and underfill material properties on the device performance as well as the structural reliability is examined. Numerical simulations reveal that the magnitude of n-type carrier mobility change correlates with the increase in the underfill CTE and modulus as well as microbump pitch and height, but the decrease in the microbump radius. The crack driving force dependence on material property and geometry differs from that of mobility change. While the driving force is crack location dependent, the greater crack driving force corresponds to larger underfill CTE and bump radius, but smaller underfill modulus and microbump pitch.

This study focuses on the impact of chemical solutions (hydrogen fluoride and tetramethylammonium hydroxide) on the change in properties of advanced porous low-k films. It was shown that there is no preferential removal of methyl groups during the dissolution process. With regard to wetting agents, the presence of isopropyl alcohol or surfactant (polyoxyethylene ether and alkoxylated diol type) in HF solution slowed down low-k film etching. Complete removal of surfactant residual usually requires an additional rinsing step using a low-molecular weight alcohol such as isopropyl alcohol.

Chemical Mechanical Polish (CMP) is one of the key technologies for the development of modern high performance integrated circuits. The requirements for the CMP uniformity get extremely demanding in order to meet the litho requirements for 32nm technology node and beyond. In this paper, two kinds of orders related to the stressor films that affect the CMP uniformity are revealed. The first is the stressor films deposition order according to the CMP polish rate of each stressor film. The second is the stress gradients order that formed inside the films sitting on top of the stressors. Through the optimization of the order, we show successfully removal of couple hundreds angstroms stressor step heights within 300mm wafer range. The method developed here can also find applications in microelectromechanical systems and 3D integration circuits.

We discuss the principles of Optical interconnects, and discuss the potential of silicon photonics to provide all the necessary building blocks to construct dense, high-bandwidth, lowpower optical links. We discuss waveguides, wavelength division multiplexing, modulators and photodetectors. We also take a look at the options for implementing light sources, a function which silicon cannot natively provide, with a focus on implementations in the IMEC silicon photonics platform.

We report a low-cost and high-throughput method to fabricate large-area light emitting pattern via thermal evaporation of organic molecules on the patterned self-assembled monolayer of homogenous 3-aminopropyltrimethoxysilane. This method is based on the selective deposition of the organic light emitting molecules on the template of self-assembled monolayer (SAM), which is patterned with nanoimprinting lithography. The selectivity can be controlled by adjusting the design of the pattern, the storage duration and the substrate temperature. The deposition selectivity of the molecules may be caused by the different binding energy of the molecules with the SAM and the substrate surface.

We focused on detailed evaluations of properties of the ultra-thin pore-seal layer (< 3 nm-thick), such as Cu diffusion barrier property and thermal stability. Cu diffusion into dense thermal silica and porous silica low-k which are covered with the pore seal layer was evaluated using metal-insulator-semiconductor (MIS) capacitors under bias thermal stress (BTS). Triangular voltage sweep (TVS) measurement shows that the ultra-thin layer on dense thermal silica suppresses the drift of Cu ions. The Time-Dependent Dielectric Breakdown (TDDB) lifetime of porous silica low-k covered with the ultra-thin pore seal layer results in a drastic increase of the capacitor lifetime with respect to the no-pore-seal control system (stable at 125 °C at least for 10000 s). Thermal decomposition of bulk material of the pore sealant was measured by thermal gravity (TG) test in nitrogen. Bulk material did not decompose through around 350 °C. The amount of ultra-thin pore seal layer fabricated on silicon wafer after thermal cycle stress in vacuum was measured by x-ray photoelectron spectroscopy (XPS). Amount of pore sealant did not decrease even after 2 cycles of 20 min, at 250 °C. Those results show that the ultra-thin layer, which we propose here, has a potential as a pore seal layer for porous low-k films.

This paper introduces a highly reliable Cu interconnect technology at the 32 nm node with CuMn alloy seed. A CuMn alloy liner seed process combined with a non-gouging liner has been integrated into the minimum-pitch wiring level. Stress migration fails with CuMn seed at plate-below-via structures were shut down by a non-gouging liner process. Integration with gouging liner and non-gouging liner is compared, and results of interaction with CuMn seed are discussed in this paper.

To reduce time-to-knowledge and costs associated with wafer scale processing a laboratory scale copper electrochemical deposition (ECD) system was developed for screening new organic additives which promote bottom-up fill in interconnect trenches and vias. This new setup enables working process conditions and functionality trends to be identified for open source and proprietary suppressors and levelers at leading edge feature sizes (sub 50nm). The laboratory results can then be compared to the in-line wafer scale plating tool results to ensure their compatibility. A reliable laboratory setup that can mimic the dynamic conditions found inside the wafer scale plating tool will enable the main objective of this work to be efficiently realized. The main objective is to test two previously published models describing copper fill inside the trenches by bridging the gap between fundamental electrochemical measurements and wafer scale plating results. To date this work will focus on the reliability and transferability of plating results between the laboratory setup and a wafer scale plating tool and present preliminary data using gap fill and bottom-up growth ratio as performance metrics.

Amorphous Ta-N thin films (14 and 62 nm thick) are deposited on Si substrates by reactive magnetron sputtering followed by Cu film deposition. The interlayer reaction and failure mechanism of the annealed metallization stacks are investigated by resistance measurements, xray diffraction (XRD) and detailed electron microscopy analysis accompanied with electron energy-loss spectroscopy (EELS). Amorphous Ta-N crystallizes at 600°C by a polymorphous transformation to Ta2N. The crystallized Ta2N barrier prevents Cu-Si interaction and intermixing up to 700-800°C, depending on the barrier thickness. Copper appears to be the main diffusing species and reacts with Si at the Ta-N/Si interface to form η˝-Cu3Si. Local Cu-Si reaction enhances the formation of TaSi2 precipitates. Silicon also diffuses, though at a much slower rate, to the surface and reacts with Cu. Local oxidation of Cu3Si occurs upon exposure to air, accompanied by SiO2 formation.

In this work, hydrophobic mesostructured organosilica thin films, exhibiting isolated mesopores (~ 7 nm), have been successfully deposited by spin-coating using different polystyrene-block-polyethylene oxide copolymers (PS-b-PEO) as structure-directing agents and methyltriethoxysilane (MTES) as organosilica precursor. Different ordered mesostructures (Face Centered Cubic, 2D or 3D Hexagonal and Body Centered Cubic) can be achieved by controlling different synthesis parameters. X-Ray Diffraction (XRD) and Grazing Incidence Small Angle X-Ray Scattering (GISAXS) techniques were used to investigate the mesostructure evolution through thermal and UV treatments. Swelling and shrinkage were evidenced by in-situ XRD and X-Ray Reflectivity measurements during the thermal removal of the meso-templates. Infrared spectroscopy and 29Si NMR were additionally used to investigate the microstructure evolution. The film porosity was estimated thanks to Ellipsometry Porosimetry (EP). Correlation between mechanical properties through nanoindentation measurements and the mesostructure ordering is discussed as well as assessments of the dielectric constant k by mercury contact probe.

Thin TiN films were grown on SiO2 by a reactive dc magnetron sputtering (dcMS) and high power impulse magnetron sputtering (HiPIMS) at range of temperatures from 45 to 600oC and the properties compared. The HiPIMS process produces denser films at lower growth temperature than does dcMS and the surface is much smoother for films grown by the HiPIMS process. The grain sizes of both orientations are smaller in HiPIMS grown films than in dcMS grown films. The [200] crystallites have smaller size than the [111] crystallites for all growth temperatures. For the dcMS process the grain size increases with increased growth temperature for both the [111] and [200] crystallites. For the HiPIMS process the [200] grain size increases monotonically with increased growth temperature, whereas the size of the [111] oriented grains decreases to a minimum for growth temperature of 400 oC after which it starts to increase with growth temperature.

In this paper, silver nanoparticles with a mean diameter of 40 nm are studied for future applications in microelectronic devices. The enhanced diffusivity of nanoparticles is exploited to fabricate electrical interconnects at low temperature. Sintering condition has been tuned to tailor the grain size so that electrical resistivity can be lowered down to 3.4 μOhm∙cm. In this study, a {111}-textured gold thin film has been used to increase diffusion routes. The combined effects of the substrate crystalline orientation and the sintering condition have been demonstrated to have a significant impact on microstructures. In particular, a {111} fiber texture is developed above 300°C in printed silver only if the underlying film exhibits a preferential orientation. This condition appeared as essential for the efficiency of the gold wire-bonding process step. Thus, inkjet-printed interconnects show a prospective potential compared to conventional subtractive technique and offers new opportunities for low cost metallization in electronics packaging.

This paper describes a three-step process regime for the integration of porous SiCOH based ultra low-k materials in existing copper damascene technologies. During the work with these complex and sensitive materials, it became more and more clear, that a successful patterning depends not only on the etch step but also on the adjustment between the etch and the following cleaning and k-restore processes. The presented process regime starts with a reactive ion etch process for trench patterning followed by a post etch clean to remove etch residues. Finally a k-restore process was performed to repair the damaged regions in the trench sidewalls. In this work it became clear, that the etch chemistry influences not only the results of the etch process ostensibly sidewall damage but also kind and effect of the post etch clean. Each plasma composition results in the necessity of a customized post etch cleaning solution. Finally a k-restore process using Hexamethyldisilazane (HMDS) as restore chemical was demonstrated successfully. Enhanced temperatures and an additional UV-treatment are possibilities to promote the restore effect.

Membranes of epitaxial SiC have been used as a means of eliminating the leakage current into the Si substrate during circular transmission line model (CTLM) measurements. In the n+-3C-SiC/Si wafers, the Si substrate was etched in a patterned window with dimensions up to 10 mm × 15 mm2. An array of CTLM metal contacts was then deposited onto the upper surface of the n+-SiC membrane. The CTLM contacts on the membrane have shown an ohmic current/voltage response while electrodes located on the adjacent substrate were non-ohmic. Values of ρc were measured directly on the membranes. These results have shown a significant increase in the current flow below the metal contacts due to the presence of the Si substrate.

The material properties of two ultra low-k organic polymers are characterized for copper interconnect integration. The k-values are 2.2-2.3 for both. Compared to OSG materials of similar k-values, these polymers have lower porosity and smaller pore size, achieved using selfassembled chemistry. Both materials demonstrate excellent resistance to plasma damage: no water uptake was detected after exposure to selected etching plasmas. This characteristic, combined with the small pore size and low porosity, results in the successful integration of the organic low-ks in 80 nm spacing with no significant increase in the integrated k-values.

It is found that higher open porosity in polymer A is accompanied by higher leakage current, which is not however linked to lower dielectric breakdown lifetimes.