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A Comparative Study of Nickel Silicide Formation Using a Titanium Cap Layer and a Titanium Interlayer

Published online by Cambridge University Press:  21 March 2011

W.L. Tan
Affiliation:
Center for Integrated Circuit Failure Analysis and Reliability, Faculty of Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, Singapore
K. L. Pey
Affiliation:
Center for Integrated Circuit Failure Analysis and Reliability, Faculty of Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, Singapore
Simon Y.M. Chooi
Affiliation:
Department of Technology Development, Chartered Semiconductor Manufacturing, 60 Woodlands Industrial Park D Street 2, Singapore 738406, Singapore
J.H. Ye
Affiliation:
Institute of Materials Research and Engineering, 3 Research Link, Singapore117602, Singapore
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Abstract

NiSi formation is known to be hindered by interfacial native oxide. Such oxide is easily formed on the Si surface through inefficient cleaning or a long time lag prior to Ni deposition. In this study, two methodologies were investigated to remove this layer of native oxide when no DHF clean was performed prior to metal deposition. Firstly, the deposition of a 100°C Ti cap layer after Ni deposition and secondly, the deposition of a middle 50Å Ti prior to Ni deposition. The samples were then rapid thermal annealed from 500 to 800°C. It was found for the Ti / Ni / SiO2 / Si stack, a layer of NiSi was formed starting from 600°C. Transformation to the NiSi2 phase begins at 750°C. As for the Ni / Ti / SiO2 / Si stack, a layer of NiSi was formed after 500°C annealing and conversion to NiSi2 also took place at 750°C. However, it was found that at low temperatures such as 500-600°C, facets of NiSi2 were identified under the thick NiSi layers, embedded in the Si substrate. Ternary phases like TixNiySiz were also identified at the surface of the sample.

Type
Research Article
Copyright
Copyright © Materials Research Society 2001

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References

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