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Electricaland Structural Characteristics Of Ultra-Thin TiO2/Ti-Si-O Stacked Gate Insulator Formed by Rf Sputtering Technique

Published online by Cambridge University Press:  21 March 2011

M. Koyama ,
A. Kaneko ,
M. Koike ,
I. Fujiwara ,
M. Yabuki ,
M. Yoshiki ,
M. Koike  and
A. Nishiyama
M. Koyama
Affiliation:
Advanced LSI Technology Laboratory 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
A. Kaneko
Affiliation:
Advanced LSI Technology Laboratory 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
M. Koike
Affiliation:
Advanced LSI Technology Laboratory 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
I. Fujiwara
Affiliation:
Advanced LSI Technology Laboratory 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
M. Yabuki
Affiliation:
Environmental Engineering and Analysis Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
M. Yoshiki
Affiliation:
Environmental Engineering and Analysis Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
M. Koike
Affiliation:
Environmental Engineering and Analysis Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
A. Nishiyama
Affiliation:
Environmental Engineering and Analysis Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan
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Abstract

In this paper, we have reported an attempt to decrease equivalent oxide thickness (EOT) of TiO2gate insulator by thinning the amorphous layer formed at the TiO2/Si interface. We have decreased the thickness of the TiO2/Si interfacial layer to as little as 1.6 nm by suppressing the oxygen flow rate during the TiO2 sputtering. It was confirmed that the dielectric constant of the interfacial layer revealed higher value than that of SiO2, depending on the sputtering condition. Titanium in the interfacial layer, which was responsible for the polarization enhancement, was explicitly identified by high spatial resolution TEM-EELS. As a result, EOT of 1.3 nm was realized by TiO2/Ti-Si-O stacked gate insulator without any degradation in the electrical characteristics.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 670: Symposium K – Gate Stack and Sillicide Issues in Silicon , 2001 , K4.7
Copyright
Copyright © Materials Research Society 2001

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References

REFERENCES

[1] Lee, J.C., Qi, W., Nieh, R., Lee, B., Kang, L., Onishi, K., Jeon, Y., and Dharmarjan, E., Workshop on High-k Gate Dielectrics, 2000 New Orlens, p23.Google Scholar
[2] Yamaguchi, T., Satake, H., Fukushima, N., and Toriumi, A., Technical Digest of IEDM 2000, p19.Google Scholar
[3] Jeon, Y., Lee, B.H.. Zawadzki, K., Qi, W-J., Lucas, A., Nieh, R., and Lee, J.C., Technical Digest of IEDM 1998, p797.Google Scholar
[4] Campbell, S.A., Smith, R., Hoilien, N., He, B., and Gladfelter, W.L., Workshop on High-k Gate Dielectrics, 2000 New Orlens, p9.Google Scholar
[5] Hobbs, C., Hegde, R., Maiti, B., Tseng, H., Gilmer, D., Tobin, P., Adetutu, O., Huang, F., Weddington, D., Nagabushnum, R., O'Meara, D., Reid, K., La, L., Grove, L., and Rossow, M., Symposium on VLSI Technology Digest of Technical papers, 1999, p133.Google Scholar
[6] He, B., Ma, T., Campbell, S.A., and Gladfelter, W.L., Technical Digest of IEDM 1998, p1038.Google Scholar