During the last few years, hot-wire chemical vapor deposition (HWCVD) has been explored as a low-temperature process for epitaxially thickening c-Si seeds layers on low cost substrates. Here, we demonstrate HWCVD epitaxy on thin polycrystalline silicon seed layers on borosilicate glass substrates. The crystal Si seeds are large-grained (~10 µm) polycrystalline silicon that were fabricated by Al-induced crystallization of a-Si. We report the growth of 0.5 µm of epitaxy at ~670°C.

In this paper we present the channel degradation properties of MOSFET with gate oxide grown using electron cyclotron resonance (ECR) plasma. Si was oxidized using ECR plasma of 10% O2/He at 450°C for 60 min. MOS and MOSFETs devices were fabricated, using ECR grown oxide as a gate oxide, to evaluate the electrical properties. We found that the n-MOSFET with ECR as-grown oxide shows poorer channel degradation properties, by approximately two orders of magnitude, compared to channel with thermally grown (at 950°C) dry oxide. When as-grown oxide was annealed at much higher temperature (~800oC), channel resistance for the hot carriers improved and became comparable to that of the thermally grown oxide. We have shown that because of the lower processing temperatures used during oxidation strain is present in the bulk oxide and also at Si-SiO2 interface. Annealing at higher temperature can relieve strain and this assumption was found be self consistent with the infrared absorption study.

We have investigated the shift of threshold voltage in the a-Si:H TFT due to the various negative pulse width stress. The drain bias dependent threshold voltage shift in the pulsed stress of a-Si:H TFT for AMOLED backplane is also measured and analyzed. When a positive gate and drain bias is applied to a-Si:H TFT (W/L = 200/4 Ým), VTH of a-Si:H TFT is increased during the stress time due to the defect state creation and charge trapping. VTH of a-Si:H TFT is increased from 1.645V to 2.53V (δVTH=0.885V) after the DC gate bias stress of VGS=15V, VDS=0V for 20,000sec. When the pulsed negative bias stress is applied to the gate electrode of the current driving a-Si:H TFT with the drain bias, VTH shift is considerably reduced due to the hole trapping into the gate insulator during the stress. When a negative pulse width is 16msec (pulse of 60Hz), the VTH is increased form 1.594V to 2.195V (δVTH=0.601V). When a negative pulse width increases from 16msec to 5sec without drain bias (VDS=0V), VTH is increased from 1.615V to 2.055V (δVTH=0.44V). When a drain bias is increased from 0V to 15V, VTH is slightly decreased from 1.58V to 1.529V (δVTH=-0.051V) due to large (-30V) VGD (VG=-15V, VD=15V) bias, while it is increased from 1.66V to 2.078V (δVTH=0.418V) width DC gate bias stress of VGS=15V, VDS=15V for 20,000sec.