Reliable radiometrie temperature measurement has been a major challenge in making rapid thermal processing (RTP) more widely accepted. In order to meet road map requirements involving temperature uncertainty, uniformity and control, new techniques must be demonstrated and/or existing measurement methods must be substantially improved. Critical aspects of radiometrie methods for temperature measurement are centered about the topics: radiative and optical properties of the wafers including layered systems, surface roughness effects, and reflected irradiation from lamp banks and chamber walls. The systematic method for inferring temperature is rooted in the measurement equation which relates the radiometer output to the exitent spectral radiance from the target which reaches the detector and prescribes the roles that emissivity variability and stray radiation have on the result. An overview is provided on the knowledge base for optical and thermal radiative properties. Methods for reducing emissivity and stray radiation effects are summarized. Calibration procedures necessary to assure that the in-chamber or local temperature scale is traceable to the International Temperature Scale (ITS-90) are discussed. The issues which can impact improved temperature measurement practice are summarized.

An RTP system with accurate lamp power control was used to study the repeatability of Sens Array type “1530” and “1501” thermocouple (TC) wafers. The drift of the “1530” wafers was measured over 200 heating cycles of 20 seconds at 1050 °C and 1150 °C. Over the 200 cycles at 1150 °C, a drift between -0.5 and +1.0 °C was found. Over the 1050 °C cycles a larger drift between +1.0 °C and +2.0 °C was found, possibly caused by the formation of “haze” over the wafer that changed the optical properties of the wafer. Experiments were conducted for the effect of unloading/loading of the wafer in the oven. An instability of maximum ±0.4 °C was found for “1530”, caused by the unloading/loading. The relative accuracy of “1530” from one thermocouple to another shows a typical variation of ±1.0 °C or smaller. The older technology TC wafers (1501), showed considerably higher instability upon wafer unloading/loading and higher TC to TC variations (± 5 °C). The useful lifetime of a TC wafer is at least 50 to 200 heating cycles.

Pyrometry of silicon wafers under 700°C at wavelengths over 1μm is difficult because lightly doped wafers become partially transparent. In this work, a modified commercial RTCVD reactor with 8” wafer capability was used to study the temperature measurement of Si wafers over the range of 400–700°C using top and bottom pyrometric detectors. We present initial results on measurements of both reflection and transmission in-silu to determine emissivity at 3.3μm. For heavily doped wafers emissivity was independent of temperature and the measured temperature by pyrometry agreed well with that measured by thermocouple for 400–700°C. For lightly doped wafers, emissivity was temperature dependent due to the increased transparency of the wafer at low temperatures. Using fixed emissivity, the measured temperature severely underestimates the actual temperature below 550°C. By calculating emissivity from the measured reflection and transmission, accurate temperature measurement was achieved from 400–700°C without any a priori knowledge of the wafer.

We demonstrate an interactive software system in which the emissivity of wafers can be estimated in situ using different models. The system allows the data taker to introduce a choice of design parameters necessary for the control of temperature uniformity. The objective of the interactive system is to obtain a better estimation of the wavelength dependent emissivity by using existing data such as integrated emissivity, for example, as input information. Results for some of the models are presented and compared to show differences in the models chosen. The principle advantage offered by the system are the likely prospects of a realistic improvement and confident assessment for real time temperature measurement and control in an RTP environment.

In an effort to develop an emissivity independent temperature measurement technique for the AST Rapid Thermal Processor (RTP), AST has conceived of the Hot Liner™. The Hot Liner is a silicon nitride coated silicon wafer which is permanently installed in the process chamber, immediately below the wafer. The pyrometer, which is calibrated to a production wafer, views the constant emissivity Hot Liner to produce repeatable temperatures on product wafers regardless of their backside emissivity.

Given the repeatability of the Hot Liner, the wafer temperature uniformity must then be optimized in order to achieve 0.25μm capable processing. AST has developed a methodology which incorporates process monitors (ion implanted test wafers) to establish process uniformity in addition to multiple thermocouple wafers to verify across wafer temperature uniformity. The process monitors are used to separately optimize the ramp and steady state steps in the production recipe.

Utilizing the AST methodology to optimize processing with the Hot Liner has allowed AMD to significantly improve its RTA processing. The Hot Liner greatly decreases backside and pyrometer effects which yields limited wafer to wafer variation (< 5C, 3σ). In combination with the optimization process this results in excellent within wafer uniformity (< 3C, 3σ).

Due to polycrystallization, the emissivity of amorphous silicon is known to vary during annealing at temperatures above 500°C. This transition from α-Si to poly-Si usually occurs during the ramp and the beginning of steady stages of the rapid thermal process. However, the majority of current temperature control methods in RTP neglect time-dependent change of emissivity, and the temperature profile of process calibration is different from that of real annealing process. Various kinds of wafers with in-situ doped amorphous Si are investigated using emissivity-independent temperature control. Some process parameters and material parameters, such as ramp rate and doping level, are explored to study their influences on emissivity change, and consequently on electrical and optical parameters.

Temperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses a/c lamp ripple to compensate for emissivity. Process temperatures for anneals of arsenic and boron implants were inferred from post-anneal sheet resistance, and for rapid thermal oxidation, from oxide thickness. Results imply temperature control accuracy of 12°C to 17°C at 3 standard deviations.

Simple rapid thermal processing (RTP) system configurations, in which the wafer temperature is controlled by a pyrometer viewing the wafer's backside, are vulnerable to changes in the spectral emissivity of this surface. One method for emissivity-independent temperature control is to use an opaque plate beneath the wafer as a radiation shield, which masks the wafer's backside from the heating lamps and provides a target whose temperature can be monitored easily by a pyrometer or a thermocouple. Experimental studies of the dynamic temperature responses of the wafer and the shield are in good agreement with predictions from a theoretical model based on a simple analysis of radiation heat transfer in the system. For the set of wafers studied here, pyrometer control of the shield temperature gave a spread of wafer temperatures of 4°C, as compared to a range of 160°C when the shield was not used. The radiation shield was also shown to give RTP process results which are immune to changes in wafer backside coatings.

SEMATECH has worked with numerous commercial suppliers of RTP systems on both evaluation and development projects. It has adopted standardized methods which minimize monitor wafer impact and improve system characterization. RTP temperature control requirements are projected to tighten with each successive technology node (1). This paper discusses issues concerning performance evaluation of Rapid Thermal Processors (RTP).

The spectral transmittance, reflectance and emittance of silicon related materials and structures are measured simultaneously utilizing a spectral emissometer operating at near- and mid-IR spectral range and temperature range of 300 to 1500K. Several kinds of samples have been considered here: a) SiO2/Si with oxide in the thickness range of 653–5124A, b) SiO2/Si/ SiO2 with oxide thickness of 5000A on both front and back sides c)Multi-layers of SiO2/Si/ SiO2/poly-Si, with backside oxide of 1600A and 250A, respectively and d) separation by implantation of oxygen (SIMOX), with embedded oxide thickness of 4000A. An extensive analysis has been performed to interpret and compare the results obtained from these measurements.

Concerning the SiO2/Si, we find that the experimental results are in accord with the sinusoidal relation of emissivity as a function of the silicon oxide thickness and hence the Applied Materials model. Experimental results on SiO2/Si/SiO2 are also presented here. For the multi-layers of SiO2/Si/SiO2/poly-Si, it is interesting to note that for temperatures above 600°C, the emissivity is independent of temperature and wavelength for the backside oxide thickness of 1600 and 250A. SIMOX measurements are presented as well. The Fiory model has been utilized extensively to investigate the high temperature emissivity data. The applications and limitations of this model are discussed.

Experimental studies of the room temperature emissivity of polysilicon are reported here. These measurements have been performed using a spectral emissometer operating in the wavelength range of 0.8 – 20 μm. The measured optical properties are deconvolved to yield the wavelength dependent refractive indices and extinction coefficient of polysilicon. An in house developed computer program, OPCalc, is deployed to perform these calculations. Experimental results of the temperature dependent emissivity of a-Si / SiO2 / Si / SiO2 / a-Si, fabricated on single side polished silicon substrates, in the temperature range of 300 to 1100 K have been reported here. These measurements are performed for a-Si thickness of 2100A. Comparisons of the temperature dependent radiative properties of these structures between the front and the back show that the contribution of surface roughness to emissivity is negligible- The exposure of these a-Si coated structures to high temperatures in open environment has caused these surfaces to oxidize. Interpretations, have been sought by comparisons of the experimental data with those on SiO2 / Si structures.

RTP temperature measurement using conventional pyrometric technique has serious limitations such as uncertainty of emissivity, lamp interference, and window/chamber heating effect. In this paper, we propose to compensate for these effects using a real-time computational algorithm based on physical model of pyrometric detectors and wafer temperature dynamics. We consider an RTP system for processing 200 mm wafers with five circular zones of heating lamps and ten pyrometric sensors, five of which measure the radiation from five optically isolated dummy lamps and the rest measure the radiation of the wafer back side at different radial positions. Thermocouple measurements are also used to identify the model parameters. Part I of the paper is concerned with modeling and parameter identification.

New device architectures for advanced Integrated Circuits (IC) have been studied within the frame of our GRESSI Program through the technological development of the well known but less implemented low temperature selective epitaxial Si and SiGe films. High performance IC manufacturing requirements, such as large diameter wafer uniformity, reproducibility, throughput and reliability can be met by commercial integrated processing, single wafer cluster tools.

Using an industrially available CVD single wafer reactor, special care has been taken to integrate these films into advanced CMOS and BiCMOS processes with a minimum of drawbacks. Indeed, the Si and SiGe growth rate dependence on filling ratio as well as full selectivity are major issues. The loading effect as a function of temperature, gas mixture, Ge and dopant incorporation has been studied and optimized for these applications.

Finally, device results are compared between conventional and developed architectures showing real improvements with minimum process modifications.

Si / Si1-x-yGexCy / Si heterostructures containing up to 17 at.% Ge and 1.9 at.% C were grown on (001) silicon by low pressure Rapid Thermal Chemical Vapor Deposition, using a mixture of silane, germane and methylsilane, diluted in hydrogen. The samples were then annealed in a Rapid Thermal Processing furnace, under an atmospheric pressure of nitrogen, at temperatures ranging from 900 to 1130 °C.

The samples were characterized using infrared spectroscopy and x-ray diffraction. SIMS profiling and TEM observation were performed on some of the samples.

Substitutional C gradually disappeared, either precipitating out to form cubic silicon carbide (β-SiC), or simply vanishing into interstitial positions. In any case, the in-plane lattice constant remained constant after annealing, indicating that there was no mechanical strain relaxation by formation of misfit dislocations. The perpendicular lattice constant increased due to the decrease in substitutional C concentration, as well as it decreased due to the germanium out-diffusion. This variation of the strain during annealing was modeled, and allowed the determination of the kinetics of the substitutional carbon disappearance. The same behavior was observed for all samples. Indeed, the Cs disappearance rate was always increased for samples with higher initial Ge and C concentrations. The kinetics of this precipitation was found in very good agreement with previous published results.

A comparison of SiH4 and Si2H6 chemical vapor deposition kinetics was performed in a rapid thermal processing (RTP) system at temperatures between 600 and 800 °C and reactant gas pressures between 1 and 25 mTorr. Quantitative assessment of the nucleation parameters and the microstructures of the deposited polycrystalline Si (poly-Si) films on SiO2 have been determined using in situ real time single wavelength and spectroscopie ellipsometry. In addition to ellipsometry, atomic force microscopy and cross-sectional transmission electron microscopy were used ex situ to observe the nucleation stage and the microstructures of the poly-Si films. In the present study we compare the nucleation, poly-Si film microstructure and surface roughness using SiH4 and Si2H6 in the RTP system and show that under the same processing conditions the saturation nuclei density (1010 cm−2) for Si2H6 is about 6 times higher than that for SiH4 and the poly-Si films from Si2H6 are smoother and have better columnar structure than those from SiH4.

A particularly important parameter for selective epitaxial depositions is the time for nuclei to form, i.e. the incubation time. An operational incubation time were determined from the real time ellipsometric measurements and confirmed by AFM. The incubation times for using SiH4 and Si2H6 are different, but they show similar activation energies of about Einc = 1 eV in the 600–800 °C range. A formula of incubation time tinc was obtained and expressed.

High-quality epitaxial Si1-x-yGexCy layers were grown on Si by rapid thermal chemical vapor deposition. Schottky diodes of TiW/SiGeC were fabricated using conventional Si processes. I-V and C-V measurements were performed to assess effects of crystal defects in the alloy on the electrical properties. For defective SiGeC films due to non-substitutional carbon, high series resistance and additional tunneling current were measured under forward bias, as well as leakage current under reverse bias. A transport mechanism of deep generation/recombination centers formed by carbon complexes is proposed to explain the I-V characteristics.

The growth properties of β-SiC on (100) Si grown by rapid thermal chemical vapor deposition, using a single precursor (methylsilane) without an initial surface carbonization step, were investigated. An optimun growth temperature at 800°C was found to grow single crystalline SiC. The single crystalline SiC films were used to be the buffer layers for the growth of subsequent poly Si films. For the poly Si grown at low temperature (625°C), the (110) Si diffraction was found to be the dominant peak in the X-ray diffraction spectra at the initial growth stage, while the poly Si grown on oxide was dominated by (111) texture. A small average misfit (4 %) between (110) Si planes and (100) SiC planes was proposed to explain this effect. To apply the Si/SiC/Si multilayers, SiC/Si heterojunction bipolar transistors (HBT's) were fabricated and compared to Si bipolar junction transistors.

Dual spectral source assisted MOCVD is an ideal technique for the deposition of high dielectric constant materials as well as other electronic and optical materials. Tungsten halogen lamps and a deuterium lamp are used as the sources of optical and thermal energy. Ta2O5 films were deposited at 200°C for 30 minutes and annealed at 600°C for 30 minutes have shown leakage current densities as low as 10−10 A/ cm2 for gate voltage under 5V. To the best of our knowledge, these are the best results reported to date by other researchers. The high energy photons used in the in-situ cleaning and deposition process play an important role in obtaining high quality films of Ta2O5.

Selective rapid thermal chemical vapor deposition (RTCVD) of TiSi2 is a promising alternative to the conventional self-aligned suicide (SALICIDE) process to form low-resistivity contacts to ultra-shallow source/drain junctions of deep submicron MOS transistors. The process makes use of TiCl4 and SiH4 as the Ti and Si source gases in a temperature range of 750 – 825 °C. The primary advantage of the process over the conventional SALICIDE process is that by providing sufficient levels of Si from the gas phase, junction consumption can be eliminated. Furthermore, the process eliminates wet etch and reduces the number of process steps from four to one. For the process to be compatible with CMOS manufacturing, low-resistivity TiSi2 deposition must be achieved on both source/drain junctions as well as the poly cry stalline silicon gate electrode. It is the objective of this paper to compare basic characteristics of the process on these two surfaces. The results indicate that the crystallinity of the surface on which TiSi2 is deposited can impact the nature of the deposited film. Our experimental results indicate enhanced Si consumption on polysilicon, smaller TiSi2 grains and consequently higher sheet resistance. However, the process conditions and TiSi2 thickness can be optimized to achieve consumption free TiSi2 deposition on the junctions with acceptable performance on polysilicon.

Rapid Thermal Processing (RTP) is currently well established at the < 0.5 μm nodes for implant anneal and suicide formation/anneal in logic applications. Rapid Thermal Chemical Vapor Deposition (RTCVD) is being evaluated to deposit thin nitride for the DRAM storage node dielectric. A combination RTP/RTCVD has been evaluated in the form of a cluster tool to evaluate 60 Å gate oxides. These applications of RTP are considered to be process enabling because of either improved temperature ramp control or ambient control which are not available in batch processing. However, even with these specialized applications, rapid thermal processing comprises less than 20% of the front end thermal processes in a typical 0.35 μm fab. Process and equipment issues with rapid thermal processing remain which must be overcome if it is to replace batch processing at the 0.25 μm node. Process issues which are especially critical for RTCVD processing require improved temperature measurement, high growth/deposition rate, and an efficient method of cleaning the process chamber. Equipment issues are reliability and throughput which directly affect the tool cost of ownership. In this paper, each of these issues will be addressed and compared to batch processing using a generic logic process flow.