Atomic profiles (SIMS) and cross-section TEM images of selectively etched, annealed profiles were studied for Boron energies from 20 da eV (200 eV) to 10 keV and RTP anneals at 900, 975 and 1050 C Consistent variations of dopant depth was obtained over this process range. TEM images showed evidence of lateral dopant variation near the edges of poly-Si gate structures, perhaps an effect of lateral straggling and reflection of ions from the poly mask.

Si was implanted with 115In+ ions with a dose exceeding the value of the In solid solubility. Rapid thermal annealing with W-halogen lamp was done sequentially with the wafer facing in two different positions relative to the source of the light irradiation. It has been experimentally found that short and long wavelength components of incoherent light act in a different manner on the In atom activation in Si during RTA process. The effect of In activation and deactivation caused by the RTA treatment is reversible in the temperature region of 440–1020°C. The effect of In activation and deactivation exists after thirty RTA pulses.

The principles of vacuum ultraviolet (VUV) and ultraviolet (UV) light generated from a new type of excimer lamp are described. Direct photo-oxidation of silicon at a temperature of 250°C has been investigated using a Xe2* excimer lamp operating at a wavelength of 172 nm. The induced reaction rate of 0.1 nm/min is 90 times greater than thermal oxidation at 612°C. Results will be compared to those previously obtained by a low pressure mercury lamp and conventional furnace oxidation. Ozone plays an extremely important role in the reaction enhancement which was found to be strongly dependent upon oxygen pressure with the highest rates being achievable below 10 mbar. Ellipsometry, Fourier transform infrared spectroscopy, capacitance-voltage, and current-voltage measurements have been employed to characterise the oxide films grown and indicate them to be high quality layers. The electrical properties of the as-grown films have been improved significantly by applying an additional UV/O3 annealing step. A simple model explaining the observed reduction in the leakage current after UV annealing is proposed whilst the current conduction mechanism within the films is discussed.

Device quality gate dielectric heterostructures have been prepared using a three step plasma/rapid thermal sequence [1] in which kinetic effects determine the time-temperature aspects of the processing. The steps for forming the interface and for depositing dielectric layers have been performed at low temperature, ∼300°C, by plasma-assisted processing. Following this a low rapid thermal anneal (RTA) provides interface and bulk dielectric chemical and structural relaxations, thereby yielding device performance and reliability essentially the same as obtained using higher thermal budget conventional or rapid thermal processing.

In this paper, we report the study of rapid thermal oxidation of silicon in N2O ambient using the Applied Materials RTP Centura rapid thermal processor, and N2O oxide thickness and compositional uniformities with respect to gas flow rate and wafer rotation speed as well as other process parameters. It was found that N2O oxide uniformity is strongly dependent on gas flow rate and wafer rotation speed in addition to process pressure. With optimized setting of the process parameters, excellent oxidation uniformities (one sigma < 1%) were obtained at atmospheric pressure N2O ambient. Nitrogen concentrations of such uniform oxides grown at 1050°C atmospheric pressure N2O oxidation processes were 1.7% for a 40Å oxide and 2.5% for a 60Å oxide, respectively, as characterized by SIMS analysis.

The focus of ULSI electronics is shifting rapidly towards the development and integration of various low and high dielectric constant materials. Memory manufacturers are driving the quest for integration-friendly, high dielectric constant materials, while the logic makers are seeking materials with the lowest possible dielectric constant to use as interlayer dielectrics for their multilayer backend needs. Both of these categories of materials need the highest possible level of reliability, integrability, and manufacturability in the current and upcoming real world. Strong development emphasis in improving the structural aspects of these materials is needed more now than ever before both in university laboratories and industrial R&D. An intense focus on these materials demands immediate, improved, and innovative process solutions. One key process area is the thermal engineering and processing of these materials and hence is the focus of this paper.

In this paper, we present recent results from both university and industry process development work. We compare and contrast the thermal process requirements of some enabling materials with dielectric constants ranging from 2 to more than 100. The examples in our study encompass materials such as Teflon™, PLZT, cell nitride, and tantalum pentoxide. The enhancements in the structural and electrical performance of these materials as a function of thermal cycles used either for deposition or annealing is demonstrated through various examples.

Nitric oxide rapid thermal nitridation of thin gate oxides was investigated. Oxides from 25 to 55 Å were grown in O2 and subsequently nitrided in a nitric oxide (NO) ambient using an Applied Materials RTP Centura chamber. Nitrogen incorporation and film thickness growth during NO nitridation were evaluated. Peak nitrogen incorporation was most strongly influenced by temperature and time, with moderate influence by initial oxide thickness, and no significant influence due to NO flow rate. Peak nitrogen concentrations ranged from 1 to 9 atomic percent as characterized by Secondary Ion Mass Spectrometry (SIMS) analysis. Oxide growth during nitridation ranged from 2 Å to 11 Å with no degradation in uniformity. These data were used in the design of two 40 Å oxynitride processes incorporating 2 and 4 peak atomic percent nitrogen. High quality MOS capacitors were demonstrated with these dielectrics. Performance was compared against a baseline furnace process as well as non-nitrided RTO. Throughout this work, the chamber integrity was monitored using visual inspection, minority carrier lifetime (MCLT) and surface photovoltage (SPV). No contamination, corrosion or other degradation of the process chamber was observed in over 6 months' operation with over 700 NO processes completed. The controllability, uniformity and high nitrogen incorporation of rapid thermal NO nitridation make it an attractive process for deep sub-micron gate insulators.

The use of thin nitride/oxide (NO) stacked dielectrics is common in DRAM storage node structures today. The cell capacitance can be increased without increasing the cell plate area by decreasing the thickness of the dielectric. Combinations of novel storage node structures, textured electrode surfaces, and very thin NO films (equivalent oxide thickness equal <30 Angstroms) are being characterized for use in 256 Mb and 1 Gb DRAM devices as an alternative to premature use of high k dielectric materials. However, the native oxide formed on the surface of the polysilicon bottom electrode prior to dielectric nitride deposition in a standard LPCVD furnace reactor causes the leakage current and reliability properties of the dielectric to degrade for very thin films. Using a vacuum load-locked RTCVD single-wafer reactor with appropriate in situ ammonia and hydrogen pre-deposition surface conditioning, the native oxide can be eliminated and very thin nitride films of much higher quality can be deposited. A comparison between standard batch LPCVD processing and single-wafer RTCVD for silicon nitride deposition has been done and electrical characteristics (including leakage current and time dependent dielectric breakdown) of the films have been measured. These results indicate that use of NO dielectric films may be extended 1–2 more generations of DRAM devices. This will allow more time for improving the quality of high k dielectric films.

Beryllium diffusion during post-growth annealing is investigated in InGaAs epitaxial layers. Indeed, this undesirable diffusion may occur during thermal treatments of InGaAs/lnP Heterojunction Bipolar Transistors (HBT's), which can generate a limitation of frequency performances of these devices. Epitaxial structures have then been grown, one set by Chemical Beam Epitaxy (CBE), and another one by Gas Source Molecular Beam Epitaxy (GSMBE). The post-growth Rapid Thermal Annealing (RTA) was then performed, and Secondary Ion Mass Spectrometry (SIMS) has been used to characterize the Be depht profiles.

In parallel with our experimental study, we propose two models of Be diffusion in InGaAs in the case of point defect nonequilibrium. First, a Kick-out Diffusion model considering neutral Be interstitial species and charged point defects has been studied. Then, a Generalized Substitutional-Interstitial Diffusion model based on simultaneous diffusion by Dissociative and Kick-out mechanisms is proposed. Good agreements between experimental depth profiles and simulated curves have been obtained.

Transient thermal processing is employed for implant activation, contact alloying, implant isolation and dehydrogenation during III-nitride device fabrication. We have compared use of InN, AlN and GaN powder as methods for providing a N2 overpressure within a graphite susceptor for high temperature annealing of GaN, InN, A1N and InAlN. The AlN powder provides adequate surface protection to temperatures of ∼1100°C for AlN, > 1050°C for GaN, ∼600°C for InN and ∼800°C for the ternary alloy. While the InN powder provides a higher N2 partial pressure than AlN powder, at temperatures above ∼750°C the evaporation of In is sufficiently high to produce condensation of In droplets on the surfaces of the annealed samples. GaN powder achieved better surface protection than the other two cases.

Deep levels in undoped LEC semi-insulating (SI) GaAs have been investigated by rapid thermal annealing (RTA). The GaAs wafers were annealed for 10 sec in N2 atmosphere at temperatures ranging from 500 to 800 °C. Using photo-induced current transient spectroscopy (PITS) and Hall measurement, we have investigated the behavior of various deep levels as a function of RTA temperature and the phenomenon of thermal conversion. The change and even conversion in resistivity is related not only to decrease of the EL2 and EL6 defects, but also to shallow acceptor caused by arsenic-escaping in the surface of the wafer. Choosing proper RTA temperaturte will improve the electrical properties of SI-GaAs after RTA.

Silicon-carbide offers great potential as a wide bandgap semiconductor for electronic applications. A good quality oxide dielectric will allow MOS device fabrication and in particular N-channel mosfets for their higher electron mobility. To date oxides on N-type silicon-carbide (nitrogen doped) have exhibited excellent characteristics while on P-type (aluminium or boron doped) the characteristics are poor. This paper presents results for the oxidation and subsequent nitridation of N and P-type silicon-carbide. It illustrates the role that nitrogen at the interface has in improving the trap densities and that nitric oxide provides the nitrogen well. Nitrous oxide, previously used to nitride silicon dioxide on silicon, is shown to substantially deteriorate the interface density of states for both N and P-type substrates.

We describe a new technique for producing large-grain, poly-Si thin films on low-cost glass substrates for solar cell applications. A layer of fine-grain poly-Si is deposited on metal-coated substrate followed by a grain enhancement using optical/thermal annealing at low temperatures (∼ 500 °C). The results show that in thin-layer silicon, less than 3 microns, grains can be formed in a short time (few minutes) with grain sizes larger than the film thickness. The possible mechanisms involved in this process are also presented.

Rapid thermal processing is fast emerging as a vital low thermal budget processing technique. Use of photons of wavelengths less than 800 nm in conjunction with infrared and visible photons in RTP resulted in the reduction of microscopic defects and processing time. Screen printed back surface field (BSF) contacts and ohmic contacts which are an integral part of solar cells were processed and Schottky barrier diodes were made. Cycle time was reduced from 172 see's to 108 see's in the case of back surface field contacts and from 162 see's to 122 see's for the ohmic contacts. The Schottky diodes were characterized for electrical data. The structural properties of the metal silicon interface have direct correlation with the electrical properties of the device.