Comparison of anneal temperatures, sheet resistance, gate to source/drain leakage current, and implant pre-amorphization are studied for a conventional 2-step cobalt salicide process and a TiN capped cobalt salicide. The TiN capped cobalt silicide process is found to be superior to the conventional cobalt salicide process in producing lower sheet resistance and tighter sheet resistance distribution. The use of a TiN cap also suppresses Si out diffusion, which can prevent shorting between the gate and source/drain areas when pre-amorphization of Si substrate is used to enhance silicidation. The metal residue on oxide and nitride substrates after metal anneal and metal etch are compared using total reflection x-ray fluorescence. It is found that both Ti and Co residue on silicon nitride is higher than on silicon oxide after metal anneal and metal strip.

Platinum Silicidation involves interdiffusion of Pt and Si which finally results in the formation of PtSi. The quality of Platinum Silicide strongly influences the electrical properties such as schottky barrier height and its contact resistance. We demonstrate a two step process using rapid thermal processing (RTP) with 400 °C 30 sec silicidation in N2 atmosphere, followed by 500 °C 30 sec oxidation in O2/N2 mix. The two temperature step process gave better electrical and material characteristics compared to a single step silicidation at 400°C with N2/O2 mix. The two step silicidation recipe also had lower sheet resistance, no unreacted platinum (based on X-ray diffraction analysis) and uniform SiO2 layer (based on Auger Electron Specrtroscopy) on top of silicide, to protect it from aqua regia.

Rapid thermal processing is widely applied in self-aligned Ti silicide processes for deep-submicron devices. We investigated and modeled the effects of rapid thermal processing variables (silicide formation temperature and time, and anneal temperature and time) and Ti thickness on deep-sub-micron device characteristics. The effect of Ti thickness, formation temperature and time on diode leakage and bridging due to silicide lateral growth, and its correlation to silicide thickness was analyzed; as well as the effects of these and the anneal variables on n+ gate sheet resistance, silicide to source/drain contact resistance and transistor source-drain series resistance. An expression for n+ gate sheet resistance is given, as function of anneal temperature and time, silicide thickness, linewidth and TiSi2 C49 grain size after formation, based on a nucleation density model in agreement with measurements of TiSi2 C49 to C54 transformation kinetics. The tradeoffs and process window limits are discussed, as well as trends observed when scaling down lateral and vertical dimensions. We show that for advanced technologies, the scaling of silicide thickness and linewidth narrows the process window between full C49 to C54 transformation and agglomeration temperatures. Due to the high activation energy of the C49 to C54 transformation, a process window for low sheet resistance exists only for high temperature-short time processes.

Rapid thermal annealing (RTA) induced reactions between Ti thin films and Si wafers were characterized by sheet resistance measurements. It was found that the standard deviation a of the measurements is RTA-temperature dependent, and strongly correlates with the mean sheet resistance R. A specific temperature was identified, corresponding to a sharp σ peak in the temperature regime associated with the C49-C54 TiSi2 phase transition. This temperature is characteristic of materials parameters such as Ti thickness and substrate doping species, and can be used to accurately monitor or compare the calibration of RTA systems.

An in situ rapid thermal hydrogenation (RTH) pretreatment of titanium prior to rapid thermal annealing (RTA), or RTH/RTA, is proposed as a silicide formation annealing in a CMOS self-aligned silicide (salicide) process. The in situ RTH is found to enhance silicidation, to reduce nitridation, and even to lower the resultant sheet resistance of titanium silicide.

During in situ RTH (e.g., at 550°C), amorphous Ti silicide (e.g., 15-nm thick) grows selectively on Si. Furthermore, Ti nitridation during subsequent RTA (690°C, N2, 10 Torr, 30 s) is reduced depending on RTH (H2, 10 Torr, 30 s) temperature. Accordingly, for 550°C RTH and an initial Ti thickness of 15 nm, the sheet resistance obtained at the 0.27-μm-wide n+ poly-Si gate after a phase transition annealing (800°C, Ar, 10 s) was lower (11.7 Ω /□, st. dev. = 6%) than that of conventional Ti silicide (15.8 Ω/□, st. dev. = 10%). The silicidation enhancement and nitridation reduction are related to crystal structure metamorphosis or to hydrogen interstitial incorporation in the Ti layer during RTH as observed by x-ray diffraction analysis. It is concluded that in situ RTH pretreatment before RTA is very promising as a sub-quarter-micron CMOS salicide process.

Various annealing methods for sol-gel films have been investigated. Thermal, photothermal, RTP and excimer laser annealing have been used to convert sol-gel precursor films into oxidic films. RTP annealing of sol-gel films yields better results than classical thermal annealing or excimer laser irradiation. Photochemical effects during RTP annealing contribute to obtain high-quality oxide films. The various annealing methods are illustrated by the annealing of alkoxide precursor films of tantalum, iron, nickel and yttrium.

A new emerging application area for Rapid Thermal Annealing (RTA) may be in the manufacturing of thin-film recording heads for high-density (hard disk drive, video, audio and data tape) recording. To that end we co-designed a new commercial reactor with an external electromagnet to anneal thin soft-magnetic films (nanocrystalline iron alloys) deposited on ceramic wafers of up to 150 mm diameter. The electromagnet generates a field controllable up to 660 Oe (52.8 kA/m). It is completely homogeneous in direction (i.e. fully parallel field lines) across the entire wafer area. Wafers can be annealed either statically, or while rotating (up to 120 rpm), or in two subsequent heating steps with a 90° wafer rotation in between.

Nanocrystalline Fe-Nb-Si-N layers have better soft-magnetic properties after Rapid Thermal Magnetic Annealing (RTMA) in a static magnetic field than after conventional furnace annealing in a static field. Temperature-programmed resistance measurements and Transmission Electron Microscopy (TEM) show that the first nanocrystalline, body-centered cubic iron grains start growing already as of 350 °C from the amorphous as-deposited film, whereas the desired segregation of NbN starts only as of 530°C. RTA can be used to promote the kinetics of the segregation of NbN along the boundaries of nanocrystalline iron nuclei. This prevents the iron grains from further growth: with RTMA the iron alloys show smaller nanocrystalline iron particles (order: 10 nm) as observed by TEM.

The formation of Si-SiO2 interfaces for 40–60Å rapid thermal CVD (RTCVD) MOS gate oxides has been studied, using cluster tool technology. SiH4/N2O chemistry is used to deposit stoichiometric oxides. In-situ thermal treatments, prior to oxide deposition, typically at 800–900°C, 30–60 sec, and 50 Torr. are conducted using O2, N2O, SiH4, NH3, HCl/N2 and HCl/O2. The effect of gas flow ratios during temperature ramp-up for RTCVD interface formation is also studied. This paper presents a new quick-turnaround approach for non-destructive evaluation of Si-SiO2 interface quality for fully fabricated devices, in terms of interface charges and surface roughness.

The influence of HCl on the quality of gate oxides grown by rapid thermal oxidation has been investigated. HCl was added to oxidation ambient for some rapid thermal oxides while for others the silicon surface was annealed in a partial HCl ambient prior to rapid thermal oxidation. Improvements in gate oxide integrity were monitored on MOS capacitors and MOSFET devices by I-V and C-V testing. The levels of chlorine incorporated in the oxide from the addition of HCl to the process was measured by secondary ion mass spectroscopy. Atomic force microscopy was performed to measure surface roughening during HCl pre-oxidation treatments.

Silicon nitride, a celebrated dielectric material in semiconductor processing, is used extensively in almost all of today's key technologies (DRAM, microprocessor, SRAM, Flash memories, etc.). The physical and electrical properties of this material are well understood, and integration of silicon nitride in a given process is simple. As a result of these benefits, alternate dielectric material technologies have found limited acceptance. As feature sizes shrink, the formation of reliable thin nitride films is critical and the performance of these nitride films is very dependent on the technology used for their preparation. In this paper, we show that an incremental and overall improvement in the physical and electrical properties of nitride films can be attained by using rapid thermal processing technology.

We present the nucleation behavior of the <100 Å nitride films on polysilicon surfaces. We investigate the integrity of these films as a function of predeposition environment and discuss the oxidation and punch-through resistance of cluster tool-deposited films. The results of our studies of the conduction mechanism in thin silicon nitride films and scaling limits for these films are shown. We also discuss the structural and electrical changes these films undergo during the subsequent reoxidation process performed for leakage current reduction.

The incorporation of bonded nitrogen into ultra thin SiO2 gate dielectrics has become an important technology issue. Nitrogen atoms bonded in the immediate vicinity of the Si-SiO2 interface improve device reliability in n-channel field effect transistors. N- atom incorporation at the monolayer concentration range has been achieved by remote plasma assisted oxidation in N2O at 300°C. The incorporation mechanism and the stability of bonded-N are discussed.

In this paper, the applicability of the charge-to-breakdown test for characterisation and comparison of differently grown ultra-thin gate dielectric films is considered. It is shown that the charge-to-breakdown parameter cannot be reliably used, because it is related to the electrons tunneling through the film, and not to the mechanism of positive charge accumulation which leads to time-dependent breakdown. It is found that the constant-voltage stress provides a consistent set of stress field vs time-to-breakdown data. Nitrided gate dielectrics show improved breakdown characteristics, compared to standard silicon-dioxide films.

With the requirement for reduced dielectric thickness and improved durability in silicon MOS devices, new growth techniques and material composition are constantly being developed. An important part of this development is the electrical characterisation of the dielectric material and in particular the properties of the dielectric-semiconductor interface.

This paper presents a study of damage caused to the dielectrics of MOS capacitors which have been subjected to either constant current stressing or RF plasma etching. The density and energy position of fast interface states and fixed oxide charges were measured using standard capacitance-voltage techniques. These results are then compared with a new current transient technique, which has been developed to measure slow interface states having a range of response times. This new technique steps the surface Fermi level through the silicon bandgap and the resulting current transients provide information on trap response times at each energy position. The response time can then be related to the tunneling distance from the trap to the bulk silicon. This technique has provided important information about the energies and response times of traps generated in damaged dielectrics, and should prove to be a useful tool for damage evaluation in the future.

Numerous nitridation processes have been studied to obtain very thin (≤ 6 nm), reproducible and reliable gate oxides. Recent results (1,2,3) have confirmed that i) the NO molecule is the species responsible for the nitrogen incorporation at the SiO2/Si interface and that ii) the direct use of NO gas allows the gate oxide to be nitrided at low thermal budget whilst maintaining the same advantages as those of N2O nitridation. NO nitridation of very thin oxides has so far been inadequately documented in terms of incorporated nitrogen concentration at the SiO2/Si interface. It is of prime importance to control the incorporation of a few nitrogen monolayers at the SiO2/Si interface, particularly for device performances in the 0. 18μm CMOS technology. In the following we present results on the control of low nitrogen concentration in pure NO atmosphere, with particular emphasis on a method based on the re-oxidation of nitrided oxides. This method can be used in a production line thus avoiding the high costs and long characterization times associated with SIMS measurements.

Oxidation in nitrous oxide by conventional hot wall furnace processing and by rapid thermnal oxidation (RTO) has been a subject of much interest in recent years. RTO is a fundamentally different process than furnace oxidation, however, and the full effects of this type of processing on the oxidation kinetics are not well understood. Oxidation of silicon by RTO at a variety of pressures, temperatures, and oxidation gas mixtures has been studied. Although at lower temperatures (<850°C) the atmospheric pressure oxidation rate in nitrous oxide is very close to that in oxygen, at higher temperatures the oxidation rate in nitrous oxide is much lower than that in oxygen. At lower pressures in a RTO process, the oxidation rate in nitrous oxide is higher than that in oxygen. The effect of the nitrogen incorporated in the oxide acting as a diffusion barrier has been proposed as the mechanism of temperature dependence for atmospheric pressure oxidation in nitrous oxide. This does not explain the effects seen at lower pressures, however. We propose that some of the intermediate species produced in the decomposition of nitrous oxide into molecular nitrogen, molecular oxygen, and nitric oxide play a role in the initial stages of oxidation by RTO in nitrous oxide.

A single wafer cluster tool was developed. It is composed of a central robot arm wafer handler and three processing chambers: a RF PECVD chamber, a microwave after glow RPECVD chamber and a rapid thermal annealing chamber. The tool is designed to allow high flexibility, with in-situ multi-sequential processing capability. An in depth study of the deposition of silicon oxide by PECVD was performed. As unique features, it handles TEOS vapor without a carrier gas and it includes a double stage gas distribution system. The films were characterized by means of: ellipsometry, FTIRS, RBS, AES, SIMS, stress and etch rate in diluted (1:100) HF solution. Good uniformity (>98 %) was obtained. The results show that the quality of the films is most influenced by the wafer temperature and flux of oxygen. For the best condition, the following results were obtained: deposition rate of 370 nm/min., refraction index of 1.46, stoichiometry of 2.0, intrinsic stress of 1.3×109 dyn/cm2, carbon content below the AES and SIMS detection limit and low OH content. We also propose a model that fits our results.

To lower the temperature of oxide-passivation processing the high- purity ozone (more than 98 mole %) was used instead of usual thermal oxidation. Initial oxide formation on a Si(111) surface with high-purity ozone is investigated by X-ray photoelectron spectroscopy (XPS). From the comparison of the suboxides formed with ozone and oxygen exposures, it is clear that ozone forms less suboxide than oxygen. The oxidation with ozone also proceeds on the hydrogen passivated surface which oxygen molecules do not oxidize.

The effects of Al, Cu, and Ni on Gate Oxide Integrity (GOI) are evaluated in a critical process sequence relevant for current CMOS technology. The test process is designed to evaluate the GOI effect of these metals after multiple oxide growth and strip steps. This work compares oxide growth in a furnace and Rapid Thermal Processing (RTP). Wearout and E ramp measurements show that Ni contamination is detrimental for GOI only after multiple oxidations. Atomic Force Measurement (AFM) showed that precipitates (presumably NiSi2) form at the interface during the first oxidation. These precipitates are oxidized during the next oxidation and lead to oxide surface roughness and local Fowler Nordheim (FN) current enhancements. RTP results in a higher density of these defects as compared to furnace oxidation. Cu is fast-diffusing into the substrate and leads to defects only during the n+-poly process. Therefore, no influence of the oxide process variations on the Cu defect formation was found. In addition, no difference for furnace or RTP processes was observed. Cu precipitates that form at the poly/oxide interface lead to very pronounced FN current enhancements. As Al is built in the oxide structure, no electrode roughness occurs that leads to FN current enhancement. RTP grown oxides are less affected by Al contamination. Al can be removed by stripping the oxide, whereas Ni and Cu cannot.

This paper reviews the current status and problems of optical fiber temperature measurements for RTP and single wafer processing. Included is a discussion of a range of fiber based options available and currently being utilized today. The advantages and disadvantages of the options are presented. In addition new data from the use of the Ripple Technique pyrometer is presented. Included are data from AT&T (Lucent Technologies) ripple pyrometer development. Lucent Technologies is evaluating and improving the ripple pyrometer on a number of different style production RTP furnaces. Recent advances in signal processing for very low level photo diode currents in the range of 10 e-14 amps, will also be presented.

Current trends of silicon integrated circuit manufacturing demand better temperature control in various thermal processing steps. Rapid thermal processing (RTP) has become a key technique because its single wafer process can accommodate the reduced thermal budget requirements arising from shrinking the dimensions of devices and the trend to larger wafers. However, temperature control by conventional infrared pyrometry, which is highly dependent on wafer back side conditions, is insufficiently accurate for upcoming technologies. Lucent Technologies Inc., formerly known as AT&T Microelectronics and AT&T Bell Laboratories, has developed a powerful real-time pyrometry technique using the A/C ripple signal from heating lamps for in-situ temperature measurement. Temperature and electrical data from device wafers have been passively collected by ripple pyrometers in three RTP systems and analyzed. In this paper we report the statistical analysis of ripple temperature and electrical data from device wafers for a typical implant anneal process temperature range of 900 to 1000 °C.