Using electron beam evaporation, we have deposited Al on patterned SiO2 films grown on various Si(100)-based substrates and characterized the Al films by scanning electron microscopy, x-ray diffraction and transmission electron microscopy. The growth mode of Al in the via holes of the SiO2 films is found to depend on the base materials of the holes. For via holes based on Si(100) and TiSi2, Al fills the holes nonconformally, showing little Al on the side walls. The nonconformal growth of Al is useful for submicron via-hole filling because it prevents void formation caused by shadowing effect. In contrast, for holes of AlCu bases, Al grows conformally. For the Al grown in the via holes of Si(100) bases, single crystal Al with Al(110)//Si(100) epitaxial relation can be grown in the holes at a substrate temperature of 300°C.

The electrical and interface parameters of epitaxial orthorombic, textured orthorombic, polycrystalline orthorombic, and polycrystalline hexagonal structures with different initial thickness of the evaporated Gd layer are compared. The Schottky barrier height, the ideality factor, the series resistance, the breakdown voltage, the relative interfacial layer thickness, the energy distribution spectra of interface states, and the equilibrium interface charge have been evaluated from the current-voltage and capacitance-voltage measurements. The obtained results indicate that the initial thickness of the Gd layer influences much more stronger the obtained parameters through the perfection of the epitaxial layer than the crystal structure.

Silicon device performance has improved dramatically over the past two decades. During that time, the portion of total circuit delay attributable to interconnect wiring has increased to nearly half. Changes in the use of aluminum wiring and silicon oxide insulators must be considered to further improve performance.

The generation of ULSI circuitry now under development in the industry depends heavily on innovations in materials and processes to achieve significant improvements in wiring density and circuit performance. The subsequent generation places even greater demands on materials improvements for lower resistivity wiring and a lower dielectric constant insulator. Integrating materials and methods compatible with semiconductor processing while ensuring device reliability will create a significant financial challenge in addition to the technical challenge.

This presentation enumerates the interconnection challenges facing the materials scientist and the circuit designer. The ultimate limits in materials improvements are predictable and finite. Further improvements will be derived from design innovations such as treating interconnects as active rather than passive devices. Accurate physical modelling of MLM structures will complement even more complex electrical modelling. Manufacturing sciences will grow in sophistication if implementation is to succeed. The financial burden of these technical challenges will foster collaborations among semiconductor manufacturers, equipment vendors, and research universities.

Thermal stability of evaporated Pd, Pt and Rh films as reaction barriers to Au-Sn solder was studied for the application to fl1p-ch1p optoelectronic integration. Sn 1n the solder diffused preferentially Into a barrier metal uniformly to produce more stable IntermetalUc phases for all three metals. Pt and Rh exhibited sufficiently samll 1nterd1ffus1on coefficients with high activation energies 1n the temperature range of device operation (Pt: 1.35 eV, Rh: 1.95 eV). This result demonstartes the usefulness of Pt and Rh 1n practical flip-chip Integrated circuit fabrication. Aging test was conducted on fl1p-ch1p GalnAs/InP p-1-n photodiodes with Au-Sn/Pt metallization and no severe degradation was observed over 3400 h at 180 ° C. The same metallization techniques were applied 1n the fabrication of 10 Gbps optoelectronic Integrated receivers as well as quad p-i-n photodiodes for coherent optical receivers.

Reliability issues have assumed greater importance as critical dimensions in microelectronic devices have entered the sub-micron regime. Wafer level reliability tests have been performed to study the breakdown energy of aluminum. 1500Å, 3500Å, 5500Å aluminum films were sputter deposited at 400 °C on oxide-on-silicon substrates. Test structures with line widths varying from 1 μm to 10 μm were defined on the metal film. The aluminum lines were then passivated using a stacked layer of silicon dioxide and silicon nitride. Finally, the substrates were alloyed at temperatures from 400°C to 450 °C. An attempt has been made to minimize process variability effects by processing the substrates through the same process conditions as far as possible. Failure was induced by stressing the metal lines with high DC current densities and at a constant slew rate. The samples were characterized using optical and scanning electron microscopy. Failure analysis of the samples processed under the different conditions will be discussed.

Mass transport by electromigration in sputtered Cu line segments on a continuous W line has been measured using the drift velocity technique at temperatures from 166 to 396 °C. The Ta/Cu/Ta line segments are patterned by dry etching techniques. Cu mass depletion (voids) at the cathode end and accumulation (hillocks) at the anode were measured as a function of time from scanning electron microscope micrographs. The edge displacement of Cu was found to increase linearly with time. The activation energy for Cu electromigration drift velocity, which relates to the product of effective charge number and diffusivity, Z*D, is found to be 0.6 eV.

Traditional electromigration life testing is a time-consuming and often painful process, consuming many expensive samples and weeks of valuable time to collect enough data for a statistically significant conclusion. Annoying, to say the least, this often causes real problems in process development when cycle times of new products can often be measured in months. Therefore, there has been a strong incentive to search for alternatives.

Electroless deposition of planarized copper in SiO2 trenches has been carried out using Pd/Si plasma immersion ion implantation (PIII) or Pd2Si deposition to form a seed layer at the bottom of trenches. Electrical resistivity of the plated Cu is < 2 μΩ-cm for both types of seeding layers. For the PHI seeding method, we found a threshold Pd dose of 2 ×l014/cm2 is required to initiate Cu plating, and RBS analysis confirms intermixing of Pd, Si, and SiO2 improves the adhesion of the plated Cu to SiO2. Electromigration tests show both void and hillock formation under accelerated current stress testing, with an activation energy of 0.8 eV for interconnect open failure. The DC and pulse-DC median-time-to-failure (MTF) of plated Cu are found to be about two orders of magnitude longer than that of Al-2%Si at 275°C, and about four orders of magnitude longer than that of Al-2%Si when extrapolated to room temperature. Pulsed DC electromigration stressing exhibits a transition from low to high frequency behavior around 900 kHz, indicating a vacancy relaxation time much shorter than that of Al. For bipolar AC stressing, the ratio MTFAC / MTFDC of Cu is much smaller than that of Al-2%Si, indicating a different void recovery mechanism for Cu.

Ion implantation of boron and aluminium is used to passivate copper surfaces. Such a process modifies the copper only near its surface without affecting copper's desirable bulk properties. The present experiments show that implant doses as low as 1015 ions/cm2 of either boron or aluminium can reduce the oxidization rate by one order of magnitude or more compared to non-implanted samples.

Co-evaporated Cu-Ti films on thermally-oxidized Si substrates were annealed in vacuum at temperatures between 300 and 700°C. Reactions within the films and between film and substrate were monitored by Rutherford backscattering spectrometry, X-ray diffraction, transmission electron microscopy and sheet resistance. We found that, despite the competition from intermetallic compound formation, the Cu-Ti films react with SiO2 beginning at 400°C, with Ti migrating to the SiO2 interface to form both a suicide, Ti5Si3, and an oxide and to the free surface to form additional oxide. The reaction leaves relatively pristine Cu. Above 600°C, however, Cu begins to react with the underlying suicide. By comparison, pure Ti reacts with SiO2 only above ∼700°C.

The effect of a TiW capping layer on the mechanical behavior of AlSi(l%)Ou(y2%) thin films was evaluated. The aluminum films studied were deposited at temperatures ranging from 150 to 450°C, on various barrier layers (Ti, TiW, and TiN). Measurement of the stacks stress during anneal up to 450°C revealed that for films deposited at 150°C, the capping layer improved yield strength regardless of the type of barrier layer used. The uncapped stacks exhibited the traditional behavior of hillock formation during heating, and hillock /grain collapse during cooling. The capped stacks, however, showed considerably reduced, or suppressed hillock formation during heating, and active tensile stress relief mechanisms during cooling included cracking, voiding, and grain boundary grooving. These observations correlated well with XRD data characterizing the extent of tensile stress buildup in the aluminum films. For films deposited at 300°C, grain deformation during cooling after deposition presumably caused hardening which prevented cracking as well as changes in texture during anneal. This was observed regardless of the presence of a capping layer. Although the stacks studied were unpassivated, this data suggests that capping. layers may enhance stress migration issues in integrated systems.

The evolution of modern integrated circuit technology to sub micron dimensions has brought about a number of challenges, specially in the field of metallization. Decreasing junction depths have imposed stringent demands on the materials used for the electrical contacts. This is due to the potential interactions between the contact metal and silicon (or suicide in the case of salicide processes) causing junction leakage and/or shorting. The solution most commonly applied to this problem is that in which a barrier material is interposed between the metallization and the contact. The material most often selected for this purpose has been TiN. TiN can be deposited via the reactive sputtering of Ti in a N2 atmosphere or it can be also obtained by sputtering Ti and then reacting it with either N2 or NH3. Shrinking VLSI dimensions have brought about the need for improved planarization for the purposes of metal definition. It has also prevented the tapering of contacts for space saving reasons. Both of these issues resulted in deep, straight wall contacts with aspect ratios greater than 1 that cannot be metallized appropriately with conventional sputtering techniques. These requirements have driven the development of a conformai CVD TiN barrier process. This paper describes the evolution of the TiN metallization barrier from the requirements of 1.2μ to 0.35μ technologies.

Tungsten-rich W-Ti (or W-Ti-N) alloy films are known for their applicability as diffusion barriers in advanced silicon technology, especially in the case of aluminium-based metallizations. For a wide variety of deposition conditions and post-deposition anneal treatments these refractory-metal barriers show a columnar microstructure. In contact with aluminium the W-Ti films do not form absolute barriers, because of mutual diffusion resulting in compound formation. The reactivity of the W-Ti barriers with the Al99Si1 interconnect has been studied by in-situ resistance measurements in vacuum at temperatures of approximately 450 °C (for W-Ti alloy films) and 475 °C (for W-Ti-N alloy films). In this paper new results dealing with the relationship between deposition conditions, microstructure and barrier properties will be discussed. Furthermore, it will be shown that the actual distribution of the titanium atoms in the tungsten matrix has a substantial influence on the reactivity of the barrier film with the Al99Si1 interconnect.

In situ optical emission spectroscopy studies of Ti/TiN reactive sputtering were carried out in a Varian M2000 cluster tool. Deposition rates of Ti/TiN films at 4.3 mTorr are directly proportional to ratio of Ti(365)/Ar(435) emission lines. Measurement of the ratio of the N(655)/Ar(435) emission lines indicates an incubative dependence on.nitrogen flow due to nitridation of the target. TiN reactive sputtering is accurately described by a mathematical model based on the nitrogen flux balance on target and wall/shield at steady state.

The effect of copper content on the reaction growth and morphology of Al12W in Al-Cu/Ti-W bilayers was studied with plan view and cross-section transmission electron microscopy. After heat treatment at 450°C for 30 minutes, a spiked growth of A112W penetrated into the grain boundaries of Al-0.5 wt.% Cu film by the reaction of Al with the Ti-W sublayer. Increasing copper addition from 0.5 to 1.5% inhibited the spiked growth of AI12W, resulting in a flat and planar layer (-150Å) of Al12W. It is suggested that increasing copper segregation in the aluminum grain boundaries during heat treatment at 450°C causes a significant change in the growth morphology of the Al12W compound.

An experimental design method was used to define the process behavior of the two barrier metal properties most applicable to semiconductor device fabrication: contact resistance and contact junction current leakage. Instead of using basic research-level evaluations such as sfoichiomefry and film composition, we attempt to optimize titanium nitride (TiN) barrier metal properties to obtain both low contact resistance and low contact junction current leakage. The optimization was based on TiN films made using a rapid thermal process (RTF).

Our study focussed on TiN barriers formed on arsenic-doped n-type contacts. A two-step thermal process was used with temperature and duration of each step and the initial titanium thickness chosen as process variables. Response surface modeling of the contact resistance and contact junction leakage current reveals response variations that suggest three regions of film formation. The model defines an optimum barrier metal process to minimize both contact resistance and current leakage for the arsenic-doped contacts used for this study.

High quality barriers of sputter deposited titanium nitride (TiN) are critical elements of advanced ULSI integrated circuits. We have examined the effect of eight variables on eight parameters which may affect device characteristics and the ability to incorporate TiN into the production process. We will discuss the interaction of the variables with the properties of the deposited TiN and indicate in particular the combination of variables which lead to optimum barrier properties.

The electrical properties and structure of reactively sputtered titanium nitride barrier metal films have been characterized. Junction leakages and yields for different post deposition treatments of the barrier metal layer are reported. TEM, x-ray diffraction and Auger electron spectroscopy have been used for the physical characterization of the TiN films.

The advance of microelectronic devices has emphasized the important role of contact metallization. Contacts have become more and more complex in their structure. In this review we present some of our work on three different types of contact systems consisting of a unicomponent/bicomponent interface. The systems are: 1) alloy films (codeposited two metals) on Si, 2) a metal on Si1-xGex epilayers, and 3) a metal on a compound semiconductor (GaAs). Due to applied heat-treatments, competitive interfacial reactions take place between the various constituents of the contacts. These interfacial reactions can affects the properties of the contacts and their stability and reliability.

The thermally-induced Co/SixGe1-x reaction has been studied for a series of isochronal (25–600°C/20 min) and isothermal (600°C/u-240 min) annealing sequences using Rutherford backscattering spectrometry, transmission electron microscopy and sheet resistance measurements. Annealing at 600°C yields a reacted surface layer comprised of Si-rich CoSixGe1-x, Ge-rich SiyGe1-y and possibly CoSi2, with the two former constituents exhibiting a degree of epitaxial alignment with the substrate. The formation of Co/SiSixGe1-x alloys is discussed in terms of the ternary phase diagram.