A strong relationship between growth initiation temperature and resulting growth morphology has been observed in liquid phase epitaxy (LPE) of PbSe on BaF2. High quality epitaxial layers are consistently produced when growth is initiated between 600 and 660 degrees centigrade. This condition for epitaxy correlates with formation of a binary barium-selenide layer on the substrate surface resulting from a reaction between selenium and BaF2. This reaction, corraborated by visual observation and Auger electron spectroscopic (AES) analysis of the reaction product, occurs prior to PbSe layer growth when the substrate is exposed to selenium vapor as it is positioned under the growth solution. A barium-selenide reaction layer on a BaF2 substrate can catalyze nucleation by reducing deposit/substrate interface energy and or by increasing substrate surface energy. Such epitaxy-enabling substrate surface reactions can also occur during vapor deposition of IV-VI semiconductors on BaF2 substrates and may explain the widely observed epitaxial temperature phenomenon.

Epitaxial growth of NiSi2 on BF2+-implanted (O0l)Si at low temperatures has been studied by both cross-sectional and planview transmission electron microscopy. In implanted regrown samples with a 30-nm-thick Ni layer, epilaxial NiSi2 was found to form at a temperature as low as 250 °C. The dominant phase was observed to be NiSi in samples annealed at 400-700 °C. The final structure of the silicide layer was found to depend critically on the thickness of tile starting Ni overlayer and the annealing temperature. The presence of B and/or F atoms in silicon was found to be essential for the tormation of epitaxial NiSi2 on crystalline silicon at 220-300 °C. In addition, tile amorphicity of the substrate was also found to play an important role in promoting the formation of polycrystalline NiSi2 at low temperatures.

We predict, on the basis of ab-initio total energy calculations, that epitaxial growth of I-VII compounds on III-V substrates can be accomplished (see Fig. 1). We suggest specific combinations of I-VII materials and III-V substrates that minimize lattice mismatch and structural energy cost and show that the interface dipole can be minimal (see Table I). This makes zinc-blende I-VII materials potential candidates for passivating layers, solid state laser applications, III-V window material and hole traps. The work is published in Reference [1].

In situ x-ray photoelectron spectroscopy (XPS) is used to study the nature of the bonding at CdTe/InSb and ZnSe/GaAs interfaces grown by molecular beam epitaxy. A comparison of the In3d core level features from the InSb epilayer surface, a Tereacted InSb surface, very thin (a few monolayers) CdTe/InSb epilayer/epilayer heterostructures and from separately grown (In,Te) epilayers, indicate similar In bonding characteristics for the Te-reacted layer, the CdTe/InSb heterostructures and the (In,Te) epilayers. A parallel XPS study of ZnSe/GaAs interfaces leads to the conclusion that there is a general tendency for the formation of a III-VI interfacial compound when forming IIVI/ III-V junctions.

We report studies of the interface formed when InSb is deposited onto a CdTe substrate in a molecular beam epitaxy chamber and elucidate conditions under which epitaxial growth is possible. We find that a necessary condition for epitaxy at a substrate temperature Ts is that the growth rate exceed a minimum value Ωmin(Ts). Reflection high energy electron diffraction patterns taken in situ and transmission electron micrographs taken ex situ show that interfaces formed when Ω > Ωmin have a short period roughness which is independent of the Sb/In flux ratio and which diminishes with increasing Ω. Raman spectra show no evidence of interfacial compounds. An analysis of Auger spectra of thin layers of InSb grown on CdTe indicates the existence of Te at the surface of the InSb but not in the layer itself. The Te concentration is found to decrease with InSb layer thickness. We propose a model based on a competition between the reaction of free In and Sb with the CdTe surface and the nucleation and growth of InSb. We use this model to account for the existence of Omin, interface roughness, and the presence of Te at the surface of the InSb epilayer.

We have investigated effect of annealing at the interfaces of GaAs/ZnSe heterostructures, grown by OMVPE using TEGa, TBAs, DEZn and DMSe sources. For this work, we have annealed single quantum well (SQW), double quantum well (DQW) and super-lattice (SL) of GaAs/ZnSe heterostructures up to 640°C and characterized them by double crystal x-ray and photoluminescence. X-ray rocking curves of all these heterostructures showed a main peak due to diffraction from effective lattice parameters of epilayers and 5 satellite peaks in addition to one sharp peak from GaAs substrate. After annealing upto 640°C FWHM and position of these peaks remain unchanged, however peak height increases and small satellite peaks become more sharp and clear. Photoluminescence of these structures showed luminescence from Cu-Green and self-activated (SA) centers of ZnSe and an intense, sharp peak from GaAs. Annealing at up to 640°C did not much affect the PL intensities except that relative peak intensities of Cu-Green and SA centers showed variation which is interpreted in terms of migration of VZn and nearly no significant interdiffusion between GaAs and ZnSe layers. These factors suggest that these heterostructures are stable such that interdiffusion at interfaces is not very appreciable against thermal treatment upto 640°C and hence they are of potential importance for device applications.

MgO was deposited on different planes of sapphire substrates by Molecular Beam Epitaxy (MBE). Cross-sectional specimens from these systems were prepared and investigated by high resolution electron microscopy (HREM). Two different orientation relationships were obtained for MgO films deposited on the differently oriented sapphire substrate. Misfit dislocations at the interface in each case were analyzed. MgA12O4 (spinel) forms at the MgO/A12O3 interface by a solid state reaction under electron beam irradiation.

Interdifussion studies were performed on high-Tc superconducting multi layer structures. As substrates, Si(lll)/NiSi2/ZrO2, Si(lll)/ZrO2, Yttria Stabilized ZrO2 (YSZ), SrTiO3, MgO, A12O3 and LaA1O3 (100) single crystals were used. Also interface studies on YSZ(100)/YBa2Cu3O7-x/PrBa2Cu3O7/YBa2CU3O7-x and A12O3/PrBa2Cu3O7/ YBa2Cu3O7-x multi layer structures were performed. It is shown that the combination of different surface analysis techniques yields detailed insight in effects of reactions, diffusion and segregation on the structure and composition of interfaces in high-Tc, superconducting multi layer structures.

The reactions of titanium on germanium were studied using Raman spectroscopy and X-ray Absorption Spectroscopy (XAS). Samples used in this study were produced in a custom MBE system with dual E-gun sources, two filament sources, and base pressure <1x10−10 Torr. Ge(100) substrates were prepared by chemical cleaning and homoepitaxial deposition of 500Å - 1000Å Ge at 550°C. Ti was deposited and subsequently annealed at 50°C intervals from 500°C to 700°C. Raman and XANES spectra of the titanium germanides were obtained and used to examine the.evolution of the crystalline structures which form by the interface reactions of Ti on Ge. A low-order phase formed by diffusion controlled growth prior to the formation of TiGe2 (isomorphous with TiSi2 [C54]) by nucleation controlled growth.

We present results on the analysis of the interdiffusion process of discrete GaAs layers into a semiinfinite InGaAIP halfspace using Si doping as an agent for enhanced interdiffusion. Very strong segregation and preferential bonding phenomena are observed, resulting in extensive defect formation and loss of lattice match at the virtual interface.

Ag thin films of 90 nm in thickness were deposited on (001) GaAs substrates, with or without an amorphous Ta-Si-N cap layer on top. All samples were annealed at 550°C for 30 min in an Ar flow. The interaction between the Ag film and the GaAs substrate is characterized by MeV 4He backscattering spectrometry, scanning electron microscopy and cross-sectional transmission electron microscopy.

Without encapsulants, As is lost by sublimation and Ga-oxide forms on the Ag surface during the annealing process. Elongated prismatic triangular pits bounded by GaAs {111} planes develop in the substrate that are filled with Ag. Also, the native oxide between the GaAs substrate and the polycrystalline Ag layer balls up after annealing. No Ag-Ga or Ag-As compound is produced. With a Ta-Si-N cap layer, the pits are almost totally absent, but the interfacial native oxide layer still balls up.a

The lattice relaxation of strained Si1-xGex layers on Si (001) substrates has been examined. Single layers having a nominal composition of x = 0.14 were grown by Molecular Beam Epitaxy to thicknesses of 0.5, 1.0 and 1.5 μm, all of which are greater than the critical thickness where misfit-dislocation generation commences. Double-crystal and white-radiation topographic methods were used to reveal the misfit dislocation structure and distribution. The misfit dislocations were shown to extend from heterogeneous nucleation sites along the four available <110> directions in the plane of the interface. A symmetric distribution of dislocations between the orthogonal < 110> directions was observed. Secondary branching of the misfit dislocations was also observed which accelerates the relaxation process.

Strained Si1-xGex multilayers were deposited heteroepitaxially at 625°C on patterned oxide Si substrates using a VLPCVD (Very-Low-Pressure Chemical Vapor Deposition) reactor. Undoped Si1-xGex. layers were commensurate for Ge contents up to 23 at.% and exhibited a peak in growth rate at 8 at.% Ge. Both n-type and p-type in-situ doping were accomplished in layers having 20 at.% Ge without degradation of epitaxial quality. Arsenic and boron chemical concentrations near 1020cm−3 were achieved. Growth rates of in-situ doped Si1-xGex. were unaffected by B2H1 gas but greatly reduced by AsH3 gas. Both undoped and in-situ doped muftilayers displayed a window-size dependence of misfit dislocations after defect etching.

A new technique for improving the recovery time of bipolar power devices by misfit dislocations to fast switching speed levels is described. Misfit dislocations formed in situ at abrupt SiGe/Si heteroepitaxial interfaces are used as recombination centers in the space charge regions of devices. The density of misfit dislocations was varied over a wide range by controlling the Ge concentration and the number of Ge-containing layers in both <111> and <100> orientations. The structural properties of misfit dislocations were studied by optical microscopy, TEM, and X-ray topography. Power rectifier recovery and electrical parameters, DLTS, and minority carrier lifetime were employed to evaluate the electrical behavior of dislocations with and without gold diffusion. Fast recovery times with low leakage current and forward voltage drop were achieved by the introduction of misfit dislocations. Monotonically decreasing recovery times were obtained with increasing dislocation density. For the same recovery time, introduction of misfit dislocations produced about 50% reduction in high-temperature leakage current and similar forward voltage drop compared to devices subjected to Au diffusion. The combination of dislocations and metal impurities is also investigated and found to provide an excellent mechanism for further tailoring of the recovery characteristics of power devices. In this application the metals were preferentially accumulated in the depletion region at the misfit dislocations from small background metal concentrations leading to additional reduction of recovery time, while maintaining small leakage current and forward voltage drop.

Heteroepitaxial GaAs-on-Si utilizing a Si0.4Ge0.96/Ge buffer, with a hole minority-carrier lifetime as long as ∼ 2.5 nsec is described. This is the longest minority-carrier lifetime in GaAs grown on Si reported to date by any approach. Here we discuss the microstructural aspects of this heteroepitaxial system, including a crossectional transmission electron microscopy (XTEM) study of the interface of the SiGe/Ge buffer and the role of the SiGe layer. An x-ray double crystal diffraction (DCD) study of the GaAs layers is also presented. The SiGe/Ge buffer approach to heteroepitaxial GaAs on Si is a result of two observations: (1) SiGe epitaxial layers grown on Ge are under biaxial compressive stress (from DCD) and (2) dislocations tend to bend over into the Ge substrate (from TEM). These data and a description of the heteroepitaxy of SiGe layers on Ge are presented.

AlAs/Si heterostructures grown by atomic layer epitaxy have been evaluated by transmission electron microscopy. The hetero-interface is found to be extremely abrupt as compared with the case of GaAs/Si heterostructures grown by metalorganic vapor phase epitaxy. It is also noted that atomic steps are clearly observed at the interface and that no amorphous or alloyed regions are found. At the very initial stage of growth, a three dimensional island growth mode is dominant. However, two-dimensional growth takes place after depositing only 36 atomic layers of AlAs. Two types of defects are observed in the AlAs layer: stacking faults and microtwins. Although the density of these defects is high, they tend to self-annihilate at the interface between the AlAs layer and the upper GaAs thick layer. These results lead us to conclude that using an AlAs layer grown by atomic layer epitaxy as a buffer layer is very promising for achieving high quality GaAs/Si heterostructures with low defect density.

High quality GaAs films have been deposited on sawtooth-patterned (0.2 μm period) Si substrates by MOCVD. Three inch diameter Si wafers were patterned using a combination of holographic lithography and wet chemical etching. A two-step deposition process was used resulting in planar films with surface morphology comparable to films deposited on unpatterned substrates. The initial low temperature nucleation layer was found to be amorphous and conformed to the patterned Si surface. Rapid thermal annealing and thermal cycle growth resulted in substantial reduction in the threading defect density. The MOCVD growth and characterization of these films and the possible mechanisms responsible for the reduction/elimination of the defects at the GaAs/Si interface are discussed.

It is demonstrated that, using a suitable GaAs1-xPx buffer layer, stress free GaAs can be grown on Si (100) substrates. In fact the lattice mismatch between GaAs and GaAs1-xPx will introduce a (100) biaxial compressive stress component in the GaAs top layer. The magnitude of this lattice mismatch induced stress can be monitored from 1 to 7 Kbar by varying the P content of the buffer from × = 0.02 to × = 0.15. Results on GaAs/ GaAs1-xPx/ Si (100) ( but also on strained GaAs grown on GaAs1-xPx/GaAs(100)) are discussed in the light of photoluminescence and X-ray diffraction experiments. It is shown that, by adjusting the P composition in such buffer, the lattice mismatch induced stress can exactly compensate the thermoelastic stress, leading thus to an almost stress free GaAs at room (300K) or at low (2K) temperature.

GaAs is grown by molecular beam epitaxy (MBE) on composite GaAs-SiO2 nucleation layers fabricated on Si substrates. The composite surface (CS) is formed by an initial deposition of GaAs islands by MBE, followed by oxidation of the bare Si regions surrounding the islands. The oxidation is performed at 265°C in the afterglow of a microwave induced plasma. The fabrication of the composite GaAs-SiO2 nucleation layer is compatible with the epitaxy process. GaAs growth on CS's is performed to study the seeded lateral overgrowth of GaAs on the SiO2. We find single crystal GaAs on SiO2 regions up to 50 nm wide. On the SiO2 a large density of twins is present. The GaAs seeds are not pseudomorphic and misfit dislocation segments constitute a source of threading defects. The potential of the technique for GaAs-on-Si improvement is discussed.

GaAs grown on silicon on sapphire (SOS) offers a major advantage over GaAs on Si because of the closer match in thermal expansion coefficients. In this paper, we compare MBE grown GaAs on orientated and selectively misoriented SOS with previously optimized GaAs on Si. The comparisons are made for active layer structures suitable for microwave low noise and power FET applications. Optimization of MBE growth on SOS used comparison criteria of morphology, surface defect density, X-ray spectra, electron mobility and 10K photoluminescence spectra as indicators of residual stress. MBE growth on 6° misoriented SOS produces nearly stress free layers with the incorporation of the low temperature buffer. Electrical profiles and wafer mapping of ion implanted GaAs on SOS with low temperature buffer show excellent confinement of the FET channel layer and good electrical activation.