In the present era of big data and the Internet of things (the interconnection of computing devices in the Internet infrastructure), the fabrication of mobile and other electronic devices by three-dimensional integrated circuits (3D ICs) is receiving wide attention. The concept of using 3D ICs to extend the limit of Moore’s Law of two-dimensional ICs, by combining chip technology and packaging technology, has existed for more than 10 years. However, we still do not mass produce 3D IC devices due to low yield and reliability, as well as high cost. Most problems are caused by materials selection and integration at the small scale. This issue offers a review of 3D ICs and emphasizes the materials challenges of this new technology.

The field of electronics packaging is undergoing a significant transition to accommodate the slowing down of lithographically driven semiconductor scaling. Three-dimensional (3D) integration is an important component of this transition and promises to revolutionize the way chips are assembled and interconnected in a subsystem. In this article, we develop the key attributes of 3D integration, the enablers and the challenges that need to be overcome before widespread acceptance by industry. While we are already seeing the proliferation of applications in the memory subsystem, the best is yet to come with the heterogeneous integration of a diverse set of technologies, the mixing of lithographic nodes and an economic argument for its implementation based on overall system function, and cost rather than a narrow component-based analysis. Finally, an extension to monolithic 3D integration promises even further benefits.

The mobile revolution has enabled broad applications with a faster response, small form factors, and more data bandwidth, sensing, and processing power. The industry is pursuing three-dimensional (3D) stacked integrated circuits (ICs) in order to provide higher density interconnects between chips and/or functional blocks, which translates to enhanced system performance. These value propositions are attractive, especially for wireless applications, and will likely lead to further growth of this sector. Recent progress has been reported for development of IC stacking technologies, specifically for wireless applications. However, for full high volume deployment of 3D stacked ICs, a number of technical challenges remain, including many opportunities to be addressed by material enhancements. This article reviews the state-of-the-art technology solutions used for 3D IC stacking and highlights the material properties and remaining technology challenges required to meet the demanding specifications for high volume manufacturing of consumer devices. In particular, it focuses on the electrical (dielectrics and metallic) properties of the interconnects, the thermal and mechanical properties of the integrated components, and the ultimate component level/board level reliability characteristics.

To overcome various concerns due to scaling-down device size in future large-scale integration (LSI), it is indispensable to introduce a new concept of heterogeneous three-dimensional (3D) integration in which various kinds of device chips with different sizes, devices, and materials are vertically stacked. To achieve such heterogeneous 3D integration, the key technology of self-assembly and electrostatic (SAE) bonding has been developed. The heterogeneous 3D integration technology with the SAE bonding method has enabled 3D heterogeneous stacking of different types of chips such as the compound semiconductor device chip, photonic device chip, and spintronic device chip on complementary metal oxide semiconductor chips. A 3D image sensor with extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for future automatic driving vehicles are typical examples of heterogeneous 3D LSIs which we fabricated by the SAE bonding method.

Three-dimensional (3D) integration has emerged as a potential solution to the wiring limits imposed on chip performance, power dissipation, and packaging form factor beyond the 14 nm technology node. In 3D integrated circuits (ICs), the through-silicon via (TSV) is a critical element connecting die-to-die in the integrated stack structure. The thermal expansion mismatch between copper (Cu) vias and silicon (Si) can induce complex stresses in TSV structures to drive interfacial failure and Cu extrusion, degrading the performance and reliability of 3D interconnects. This article reviews current studies on thermal stresses and their effects on reliability of TSV structures. Recent results from measurements of stress and plasticity characteristics of Cu TSV structures are reviewed, including wafer curvature, micro-Raman spectroscopy, and synchrotron x-ray microdiffraction techniques. The effects of the Cu microstructure on stress and reliability, particularly on via extrusion and the device keep-out zone in TSV structures, are discussed. Based on the analysis of the reliability impact, we explore the potential of material and processing optimization to build reliable TSV structures for 3D ICs.

With the electronics packaging industry shifting increasingly to three-dimensional packaging, microbumps have been adopted as the vertical interconnects between chips. Consequently, solder volumes have decreased dramatically, and the solder thickness has reduced to a range between a few and 10 microns. The solder volume of a microbump is approximately two orders of magnitude smaller than a traditional flip-chip joint. In contrast, the thickness of the under-bump metallization (UBM) remains almost the same as that in flip-chip solder joints. Therefore, many issues concerning materials and reliability of microbumps arise. This article reviews the challenges related to microbump materials for vertical interconnects, including transformation of solder joints into intermetallic (IMC) joints, necking or voiding induced by side wetting/diffusion on the circumference of the UBM, formation of porous Cu3Sn IMCs, early electromigration failures caused by specific orientations of Sn grains, and precipitation of plate-like Ag3Sn IMCs. An alternative way of fabricating vertical interconnects using direct Cu-to-Cu bonding is also discussed.

The field of plasmonics has transformed the ability to control nanoscale light-matter interactions with applications ranging from high-efficiency photovoltaic modules to ultrasensitive biodetectors, electromagnetic cloaks, and subwavelength integrated photonic circuits. This article summarizes my group’s efforts to contribute to this burgeoning field, with emphasis on our research in quantum plasmonics and optical-frequency magnetism. First, we explore the plasmon resonances of individual nanoparticles as they transition from a classical to a quantum-influenced regime. We then utilize these results to directly monitor hydrogen absorption and desorption in individual palladium nanocrystals. Subsequently, using real-time manipulation of plasmonic particles, we investigate plasmonic coupling between pairs of particles separated by nanometer- and angstrom-scale gaps. For sufficiently small separations, we observe the effects of quantum tunneling between particles on their plasmonic resonances. Finally, using the properties of coupled metallic nanoparticles, we demonstrate the colloidal synthesis of an isotropic metafluid or “metamaterial paint” that exhibits a strong optical-frequency magnetic response and the potential for negative permeabilities and negative refractive indices.