Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgment
- 1 INTRODUCTION TO DIGITAL SYSTEMS ENGINEERING
- 2 PACKAGING OF DIGITAL SYSTEMS
- 3 MODELING AND ANALYSIS OF WIRES
- 4 CIRCUITS
- 5 POWER DISTRIBUTION
- 6 NOISE IN DIGITAL SYSTEMS
- 7 SIGNALING CONVENTIONS
- 8 ADVANCED SIGNALING TECHNIQUES
- 9 TIMING CONVENTIONS
- 10 SYNCHRONIZATION
- 11 SIGNALING CIRCUITS
- 12 TIMING CIRCUITS
- REFERENCES
- Index
9 - TIMING CONVENTIONS
Published online by Cambridge University Press: 05 June 2012
- Frontmatter
- Contents
- Preface
- Acknowledgment
- 1 INTRODUCTION TO DIGITAL SYSTEMS ENGINEERING
- 2 PACKAGING OF DIGITAL SYSTEMS
- 3 MODELING AND ANALYSIS OF WIRES
- 4 CIRCUITS
- 5 POWER DISTRIBUTION
- 6 NOISE IN DIGITAL SYSTEMS
- 7 SIGNALING CONVENTIONS
- 8 ADVANCED SIGNALING TECHNIQUES
- 9 TIMING CONVENTIONS
- 10 SYNCHRONIZATION
- 11 SIGNALING CIRCUITS
- 12 TIMING CIRCUITS
- REFERENCES
- Index
Summary
A timing convention governs when a transmitter drives symbols onto the signal line and when they are sampled by the receiver. A timing convention may be periodic, with a new symbol driven on a signal line at regular time intervals, or aperiodic, with new symbols arriving at irregular times. In either case a method is required to encode when the symbol arrives so that the receiver samples each symbol exactly once during its valid period. With periodic signals, if the nominal data rate is known, the receiver may use a local clock source to determine when the next symbol is to arrive. In this case, an occasional transition on the signal line to correct for drift between the transmitter and receiver clocks is all that is needed to encode symbol arrival times. For aperiodic signals, an explicit transition is required to signal the arrival of each symbol. This transition may be on a separate clock line that may be shared among several signals (bundled signaling). Alternatively, this transition may be encoded on the same lines as the signal value, as with dual-rail signaling, giving a timing convention that is insensitive to line-to-line skew.
The rate at which we can send symbols over a line or through a block of combinational logic is limited by the rise time of the transmitter and transmission medium, the sampling window of the receiver, and timing noise or uncertainty.
- Type
- Chapter
- Information
- Digital Systems Engineering , pp. 394 - 461Publisher: Cambridge University PressPrint publication year: 1998