Crossref Citations
This Book has been
cited by the following publications. This list is generated based on data provided by Crossref.
Dally, W.J.
Ming-Ju Edward Lee
Fu-Tai An
Poulton, J.
and
Tell, S.
1998.
High-performance electrical signaling.
p.
11.
Kuszmaul, Bradley C.
Henry, Dana S.
and
Loh, Gabriel H.
1999.
A comparison of scalable superscalar processors.
p.
126.
Li-Shiuan Peh
and
Dally, W.J.
1999.
Flit-reservation flow control.
p.
73.
Rixner, S.
Dally, W.J.
Khailany, B.
Mattson, P.
Kapasi, U.J.
and
Owens, J.D.
1999.
Register organization for media processing.
p.
375.
Tenhunen, H.
1999.
Physical architecture of ULSI systems course development.
Vol. 3,
Issue. ,
p.
13C6/23.
Ellersick, W.
Chih-Kong Ken Yang
Horowitz, M.
and
Dally, W.
1999.
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link.
p.
49.
Henry, D.S.
Kuszmaul, B.C.
and
Viswanath, V.
1999.
The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture.
p.
256.
Zhang, H.
George, V.
and
Rabaey, J.M.
2000.
Low-swing on-chip signaling techniques: effectiveness and robustness.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Vol. 8,
Issue. 3,
p.
264.
Lee, M.-J.E.
Dally, W.J.
and
Chiang, P.
2000.
Low-power area-efficient high-speed I/O circuit techniques.
IEEE Journal of Solid-State Circuits,
Vol. 35,
Issue. 11,
p.
1591.
Pamunuwa, D.
Li-Rong Zheng
and
Hannu Tenhunen
2000.
Combating digital noise in high speed ULSI circuits using binary BCH encoding.
Vol. 4,
Issue. ,
p.
13.
Boahen, K.A.
2000.
Point-to-point connectivity between neuromorphic chips using address events.
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,
Vol. 47,
Issue. 5,
p.
416.
Tenhunen, H.
2000.
Mixed signal system design course development.
p.
1027.
Bogliolo, A.
2001.
Encodings for high-performance energy-efficient signaling.
p.
170.
Sohn, Young-Soo
Park, Jin-Seok
Sim, Jae-Yoon
and
Park, Hong-June
2001.
Full-swing CMOS output driver using on-chip capacitors,with fast rise time and small overshoot.
Electronics Letters,
Vol. 37,
Issue. 8,
p.
484.
Svensson, C.
and
Dermer, G.H.
2001.
Time domain modeling of lossy interconnects.
IEEE Transactions on Advanced Packaging,
Vol. 24,
Issue. 2,
p.
191.
Goossens, Bernard
2001.
Parallel Computing Technologies.
Vol. 2127,
Issue. ,
p.
232.
Li-Rong Zheng
and
Tenhunen, H.
2001.
Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits.
IEEE Transactions on Advanced Packaging,
Vol. 24,
Issue. 3,
p.
245.
Peh, L.-S.
and
Dally, W.J.
2001.
A delay model and speculative architecture for pipelined routers.
p.
255.
Jin-Ho Kim
Sung-Woo Han
and
Oh-Kyong Kwon
2001.
Analysis of via in multilayer printed circuit boards for high-speed digital systems.
p.
382.
Sinha, M.
and
Burleson, W.
2001.
Current-sensing for crossbars.
p.
25.
