Usual periodic scheduling problems deal with precedence constraints having non-negative
latencies. This seems a natural way for modelling scheduling problems, since task delays
are generally non-negative quantities. However, in some cases, we need to consider edges
latencies that do not only model task latencies, but model other precedence constraints.
For instance in register optimisation problems devoted to optimising compilation, a
generic machine or processor model can allow considering access delays into/from
registers. Edge latencies may be then non-positive leading to a difficult scheduling
problem in presence of resources constraints. This research result is related to the
problem of periodic scheduling with storage requirement optimisation; its aims is to solve
the practical problem of register optimisation in optimising compilation. We show that
pre-conditioning a data dependence graph (DDG) to satisfy register constraints before
periodic scheduling under resources constraints may create circuits with non-positive
distances, resulted from the acceptance of non-positive edge latencies. As a compiler
construction strategy, it is forbidden to allow the creation of circuits with non-positive
distances during the compilation flow, because such DDG circuits do not guarantee the
existence of a valid instruction schedule under resource constraints. We study two
solutions to avoid the creation of these problematic circuits. A first solution is
reactive, it tolerates the creation of non-positive circuit in a first step, and if
detected in a further check step, makes a backtrack to eliminate them. A second solution
is proactive, it prevents the creation of non-positive circuits in the DDG during the
register optimisation process. It is based on shortest path equations which define a
necessary and sufficient condition to free any DDG from these problematic circuits. Then
we deduce a linear program accordingly. We have implemented our solutions and we present
successful experimental results.