The electron thermal conductance of a dot has been calculated within a linear response theory in the regime of weak coupling with two electrode leads. Coulomb oscillations are found. We discuss the effect of the interplay between the charging energy, the thermal energy and the confinement in the behavior of the electron thermal conductance.

PECVD-grown carbon nanotubes on (100) silicon substrates have been studied and exploited for electron emission applications. The growth of CNT's is achieved by a mixture of hydrogen and acetylene gases in a CVD reactor and a 2-5nm thick nickel is used as the seed for the growth. The presence of DC-plasma yields a vertical growth and allows deposition at temperatures below 650°C. The grown nano-tubes are encapsulated by means of an insulating TiO2 layer, leading to beam-shape emission of electrons from the cathode towards the opposite anode electrode. The electron emission occurs using an anode-cathode voltage of 100 V with ability of direct writing on a photo-resist coated substrates. Straight lines with widths between 50 and 200nm have been successfully drawn. Scanning electron and transmission electron microscopy have been used to investigate the quality and fineness of the results. This technique has been applied on P-type (100) silicon substrates for the formation of the gate region of N-MOSFET devices, showing a drive current of 310μA/μm and Cox of 0.7μF/cm2.

This work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

Our observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.

We use a novel technique CABOOM – Characterisation of Alloy concentration via Beveling, Oxidation and Optical Microscopy – to visualize the change of the Ge concentration sandwiched between two SiO2 layers during the Ge condensation process. CABOOM is very sensitive to variations in the gradient of the Ge concentration in the SiGe layer and thus gives a fast and simple way to interpret the condensation process. We present a systematic study of Ge condensation in a 120nm thick Si0.92Ge0.08 layer on a 60 nm Si body SOI (silicon-on-insulator) as a function of oxidation temperature and time, using CABOOM, SIMS and XRD. CABOOM shows the non-linear variation of the Ge diffusion as a function of process time.

Although much effort has been expended toward developing alternate dielectrics for use in fabricating ULSI circuits, there is still a need for high quality SiO2 films. In particular, process temperature restrictions have increased the demand for high quality, low temperature SiO2 films.[1] Such films have multiple applications in microelectronics, including use as passivation coatings, interlevel dielectrics, gate dielectrics in metal oxide semiconductor field effect transistors (MOSFETs), thin film transistors, and in devices using dual spacers.[2] Advanced devices at the 65-nm node and beyond are typically fabricated with nickel silicided electrodes—which enable lower junction silicon consumption, lower sheet resistance, and reduced agglomeration, but require subsequent process temperatures to be below 550°C. Also, to prevent movement of the ultra shallow junctions (USJs) during a subsequent thermal cycle, the temperatures for process steps after USJ formation must be kept below 600°C. To meet these needs, we have developed a low temperature (<500°C) SiO2 process that results in excellent dielectric quality.

This paper presents results on high-quality chemical vapor deposition (CVD) SiO2 films deposited at temperatures from 200°C to 450°C using a novel proprietary and versatile silicon precursor using oxygen as the oxidizer. Composition, film stress, deposition rate, leakage current density, and step coverage results are presented.

We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

The experimental evaluation of stresses at the nanometer scale is a real challenge. We propose an innovative use of High Resolution X-Ray Diffraction to measure local strains induced in silicon by periodic arrays. This technique is non-destructive and allows for the measurement of periodic strain fields in monocrystalline silicon, created in particular by Shallow Trench Isolation process. A 0.58μm-period array of trenches filled with SiO2 gives rise to satellites in reciprocal space maps around the Si substrate peak. The intensity and envelope of these satellites depend on the local strain. The experimental reciprocal space maps are compared to those computed using the kinematical theory from the elastic displacement field calculated with finite element modelling. This technique allows us to study the generation of strain during the main steps of the STI process. During the process, after trenches get filled with oxide and top layers removed, a second diffraction peak appears with a lower intensity than the substrate one. Thanks to finite element modelling, we validate that this peak is caused by an almost constant strain in the silicon active areas. Typical values of strains after trench filling are -1.68*10-3 along × and 1.56*10-3 along z where × and z refer to transverse and perpendicular directions.

In recent years, the semiconductor industry has increasingly relied on strain as a performance enhancer for both n and p-MOSFETs. For p-MOSFETs, selectively grown SiGe alloys in recessed source/ drain regions are used to induce uniaxial compressive strain in the channel. In order to induce compressive strain effectively using this technology, a number of parameters including recess depth, SiGe thickness (junction thickness), sidewall thickness, dopant density, dislocation density, and contact materials have to be optimized. In this work, we have studied the effects of heavy boron doping and self-aligned germanosilicide formation on local strain. Raman spectroscopy has been used to study the impact of heavy boron doping on compressive stress in SiGe films. Strain energy calculations have been performed based on Vegard's law for ternary alloys and the effect of boron on strain in SiGeB alloys modeled quantitatively. It will be shown that, owing to the smaller size of a boron atom, one substitutional boron atom compensates the strain due to 6.9 germanium atoms in the SiGeB film grown pseudomorphically on silicon. The critical thickness of SiGeB has been calculated for the first time based on kinetically limited critical thickness calculations for metastable SiGe films. It will be shown that the critical thickness of the alloy increases as the boron content in the alloy is increased, making boron concentration an additional parameter for optimizing strain in the MOSFET. Based on these conclusions, boron concentration can be used to preserve the strain for thicker SiGeB films (compared to SiGe films) while keeping the dislocation density low. Furthermore, we show that NiSiGe contacts can have a profound impact on the SiGe strain. Our results indicate that NiSiGe introduces additional stress in the underlying SiGe, which further affects the strain induced in the channel