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Quantum Well Nanopillar Transistors

Published online by Cambridge University Press:  01 February 2011

Shu-Fen Hu  and
Chin-Lung Sung
Shu-Fen Hu
Affiliation:
[email protected], National Nano Device Laboratories, RDT, 26, Prosperity Road I, science-based Industrial Park, Hsinchu, Taiwan, 30078, Taiwan, +886-35726100, +886-45722715
Chin-Lung Sung
Affiliation:
[email protected], National Nano Device laboratories, 26, Properity road I, Science-based Industrial Park, Hsinchu, Taiwan, 30078, Taiwan
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Abstract

We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

Keywords

electrical propertiesnanostructurenitride
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 913: Symposium D – Transistor Scaling – Methods, Materials and Modeling , 2006 , 0913-D03-03
Copyright
Copyright © Materials Research Society 2006

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