We have carried out experiments on dual-damascene Cu interconnects with different lengths. We find that at short lengths, similar to Al-based interconnects, the reliability of Cubased interconnects improves. Also like Al interconnects, some short Cu segments do not form voids that cause failure before back-stresses prevent the further growth of voids. However, unlike Al-based interconnects, there is no apparent deterministic current-density line-length product (jL) for which all lines are immortal. This is related to the absence of a conducting refractory-metal overlayer in Cu-technology that can shunt current around small voids. Also unlike Al, we find that at long lengths a sub-population of Cu lines is immortal. We propose that this is the result of rupture of the thin refractory metal liner at the base of the dual-damascene Cu vias. As a consequence of this complex behavior, median times to failure and lifetime variations are minimum at intermediate line lengths.

Degrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions.

We have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model.

Issues associated with trench etching in low-k OSG (organosilicate glass) films for dual damascene applications and in particular for “via-first” integration scheme were the focus of this study. As a result of designed experiment in dipole ring magnet (DRM) etcher with C4F8/N2/Ar gas mixture the trench process was established with sidewall profile 89° and flat bottom. Selectivity obtained was enough to pursue etch processes using planarizing BARC (bottom antireflective coating) for additional via bottom protection. BARC fill in vias and BARC opening time were tuned to reduce generation of polymers during etch. Effective combination of dry /wet clean recipes was developed for removal of post-RIE (reactive ion etching) residues without significant changes in OSG k-value. Optimized processes were successfully used for creating dual damascene structure complying with integration requirements for 0.13 μm design rules.

We propose a modified self-aligned silicide (salicide) process that uses Ge implantation and a silicon cap to reduce the silicon substrate consumption by 75% as compared with a conventional salicide process. We have used Ge implants to increase the cobalt disilicide formation temperature. This forces the cobalt to react primarily with a deposited silicon cap, thus minimizing consumption from the silicon substrate. We expect this process to be useful for making silicide on shallow junctions and thin SOI films, where silicon consumption is constrained.

We have measured growth rates and film properties for copper CVD using Cu(hfac)2 dissolved in isopropanol as the precursor delivery method. This approach offers the convenience and control associated with liquid precursor delivery, while avoiding the need to handle the precursor at its high melting point. The method provides similar growth rates to those observed using conventional delivery by solid sublimation, with the additional benefit that these growth rates are achieved using a much lower partial pressure of precursor in the reactor. The growth rate is nearly independent of the partial pressure of Cu(hfac)2, isopropanol, and H2 over the range of operating conditions examined. The film morphology and resistivity are also largely unaffected by the deposition conditions. These results strongly suggest that the mechanism proceeds via an adsorbed intermediate formed by the reaction of Cu(hfac)2 and isopropanol, and that the surface is nearly fully saturated by this intermediate.

The impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

The microstructure of ultra-thin SIMOX depends strongly on implantation dose, energy and annealing conditions. We used TEM combined with AES and RBS to determine the microstructural evolution of SIMOX wafers subjected to various temperatures during annealing. We found that an optimum dose window to produce a continuous buried oxide layer without Si islands is 3.0-3.5×1017 O+/cm2 for 100 keV. The thickness of the silicon overlayer and BOX layer produced in this dose window was about 170 nm and 75 nm respectively. RBS analysis showed that a high quality crystalline Si layer was produced after annealing at 1350 °C for 4 hrs. The defect density was very low (< 300/cm2) for all samples implanted at 100 keV.

In the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radiofrequency plasma-enhanced chemical vapour deposition technique.

As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO2 n-MOSFETs.

In this paper, the mechanisms of the suppression of Zr-silicide formation in poly-Si/ZrON/interfacial-layer/Si structure at 1000°C annealing are discussed in detail. It was demonstrated that gaseous SiO desorption, which played a dominant role in the silicide formation in the case of the ZrO2/SiO2/Si, was completely inhibited in the ZrON/interfacial-layer/Si structure. In addition, we have found that an ultrathin interfacial SiON layer between poly-Si and ZrON stabilized the interface. Consequently, we concluded that the effective nitrogen incorporation into top/bottom interfacial SiON layers with our process was responsible for the superior thermal stability of the stack.

Chemical studies on 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) were conducted to elucidate its thermal behaviors with water and under various reaction conditions. TMCTS was heated in the presence of 316L stainless steel and in the presence of water. The heated TMCTS then was evaluated using 1H NMR (proton nuclear magnetic resonance) spectroscopy, GC-MS (gas chromatography-mass spectrometry) as a function of time, temperature and residual water concentration. The thermal degradation kinetics of gas-phase TMCTS were investigated using FTIR (Fourier transform infrared) spectroscopy at elevated temperatures. These initial results indicated that TMCTS degradation rates increased with both temperature and water concentration. This work spawned the development of a “dry” TMCTS that is expected to exhibit enhanced thermal stability relative towards uncontrolled decomposition.

The present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 < k < 2.3). It was found that the fracture energy decreases with the dielectric constant, which correlates with mechanical properties such as Young's modulus and hardness. Adhesion measurement data was also obtained for different lowk / barrier layer interfaces. The independence of interfacial fracture energy on the type of interface suggests that cohesive failure occurs in the low-k material layer and not at the interface. In addition, the very low fracture energies (G < 3 J/2) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

A study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction transistor action is reduced in single pocket SOI MOSFETs in comparison to homogeneously doped conventional SOI MOSFETs. A novel Gate-Induced-Drain-Leakage (GIDL) current technique was used to characterize the SOI MOSFETs. 2 - D simulations were carried out to analyze the reduced parasitic bipolar junction effect in single pocket thin film SOI MOSFETs.

SIMOX SOI is quite attractive for IC technology because of its potential for high-speed and low power consumption. SOI wafers are required to maintain good electrical performances in the buried oxide (BOX) layers, thus it is imperative to study the electrical characteristics of the BOX layers and the interface states. C-V and I-V techniques are very frequently utilized for extracting the parameters of the Si-SiO2 interface in bulk-silicon MOS systems. In this paper, we use a new two-terminal MOSOS (metal-oxide-semiconductor-oxide-semiconductor) structure to study the electrical characteristics of SIMOX SOI wafers. Results gained from the comparison between the experimental curves and simulation curves are presented and analyzed. We show considerable improvement in comparison with results obtained using traditional methods.

Poly(ε-caprolactone) (PCL) / poly(siloxane-silsesquioxane) (PSQ-PSSQ) nanohybrid films were fabricated. The dielectric constant of the film was scaled down from 2.66 to 2.28 when the 30% PCL was added into poly(siloxane-silsesquioxane) matrix. The FE-SEM micrograph of poly(ε-caprolactone) / poly(siloxane-silsesquioxane) (PSQ-PSSQ) nanohybrid film shows nanoporous structure. The modulus and hardness of the film decrease with increasing film thickness. As PCL content increases, modulus and hardness of the films decreases.

As device size continues to decrease, new challenges arise regarding shrinking dimensions, creating the need for thin, high-k dielectric materials, low-k dielectrics and other exotic materials. These new materials in turn create characterization issues, which cannot be resolved with traditional metrology tools. Critical structural parameters such as thickness, density, and interface roughness of a layer can be measured and monitored with X-ray reflectivity. A quick and reliable method of study regarding these materials is to base work on simulations using a very robust fitting program. This work incorporates a largely theoretical study of exotic materials of interest, including silicon oxynitride (SiOxNy), low-k (porous films) and high-k dielectrics (Ta2O5, HfO2), with a few selected experimental results.

It is known that the chemistries of hafnium and zirconium are more nearly identical than for any other two congeneric elements. Thus, both zirconia and hafnia, with the dielectric constant K > 20, have emerged as potential replacements for silica (K = 3.9) as a gate dielectric. We report an important difference between the zirconia/Si and hafnia/Si interfaces based on density functional theory calculations with the Perdew-Wang 91 exchange-correlation functional on the oxides, silicides, and silicates of Zr and Hf. The zirconia/Si interface has been found to be unstable with respect to formation of silicides whereas the hafnia/Si interface is stable. The difference between the two interfaces results from the fact that HfO2 is more stable than ZrO2 (i.e. has a larger heat of formation from its constituent elements) by more than 53 kJ/mol. The hafnium silicides, on the other hand, are less stable than zirconium silicides by ca. 20 kJ/mol.

Density functional theory was applied to simulate copper diffusion in silicon oxide, nitride, and carbide (SiOx, SiNx, SiCx). Because copper drift into oxide is significantly enhanced by negative bias, copper ions are the active diffusing species. Clusters and, in some cases supercells, modeling various ring configurations of the amorphous networks of silicon oxide, nitride, and carbide were employed. Interactions of both neutral copper and its cation, Cu+, with the network were explored. Calculations revealed a strong binding of Cu+ to SiOx, SiCx, and SiNx in contrast with neutral Cu. The Cu+ attraction to carbide clusters is significantly lower than to SiOx and SiNx, explaining the effective barrier properties of SiCx. The estimated lower bounds for activation energies for Cu+ hops between stable ring clusters of SiOx and SiNx are similar. This implies that the difference in Cu diffusion properties between oxides and nitrides is likely due to a higher percentage of large rings in amorphous oxides compared with nitrides. An approach to increasing the resistance of oxides to Cu+ diffusion is suggested.

In this work the reverse bias junction leakage was studied for Co-silicided 100 nm deep As source/drain junctions. The effect of pre-clean and silicidation temperature was investigated. The area component of the leakage current was found to be dominant for silicided source/drain areas wider than 1 mm. Increasing the thermal budget for silicidation was found to improve the area leakage. For diodes consisting of active area stripes narrower than 0.5 μm, the leakage current is no longer improved by increasing the silicidation temperature. As a result the leakage current is found to depend strongly on the active area linewidth. It was found that the linewidth dependence of the junction leakage cannot be attributed to silicide induced stress. It is argued that the higher leakage current observed for narrow lines can be attributed to the stress induced by the STI isolation and to increased silicide thickness in the narrow active lines