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Electrical Characterization of SIMOX SOI Wafers with MOSOS C-V Measurements

Published online by Cambridge University Press:  01 February 2011

C.L. Li
Affiliation:
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, PRC
Y.H. Yu
Affiliation:
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, PRC
M. Chen
Affiliation:
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, PRC
S.C. Zou
Affiliation:
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, PRC
Sh. X
Affiliation:
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, PRC
Z.X. Lin
Affiliation:
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, PRC
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Abstract

SIMOX SOI is quite attractive for IC technology because of its potential for high-speed and low power consumption. SOI wafers are required to maintain good electrical performances in the buried oxide (BOX) layers, thus it is imperative to study the electrical characteristics of the BOX layers and the interface states. C-V and I-V techniques are very frequently utilized for extracting the parameters of the Si-SiO2 interface in bulk-silicon MOS systems. In this paper, we use a new two-terminal MOSOS (metal-oxide-semiconductor-oxide-semiconductor) structure to study the electrical characteristics of SIMOX SOI wafers. Results gained from the comparison between the experimental curves and simulation curves are presented and analyzed. We show considerable improvement in comparison with results obtained using traditional methods.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

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