It is well known that the resistance to electromigration of aluminum-based interconnects is enhanced by alloying with copper. The mechanism is thought to involve the segregation of copper to the grain boundaries. The copper concentration at grain boundaries has been measured in well annealed alloys, with the compositions A1-0.5wt% Cu and AI-2wt%Cu using a VG HB5 STEM. The grain structure was stabilized by an anneal at 673K for one hour and the grain boundaries were loaded with copper by an anneal for 90 hours at 503K. It was found that the copper concentration varied from boundary to boundary. With the assumption that the copper was concentrated in a single layer the saturation concentration of copper was found to be in the range 0.025 to 0.25. This corresponds to an enhancement of the copper concentration relative to that in the grain interiors by a factor in the range between 3 and 30. The higher value approaches the copper concentration which would correspond to a monolayer of theta phase. Extensive surface segregation, amounting to a monolayer equivalent was also detected.

Near-bamboo interconnects are susceptible to failure either at polygranular clusters or within bamboo grains (transgranular failure). Polygranular failure mechanisms are often dominant in lines with near-bamboo structures at test conditions, but at service conditions, transgranular failure mechanisms are expected to dominate. In order to study the temperature and current density dependence as well as the crystallographic dependence of these transgranular failure mechanisms, it is necessary to isolate them from other mechanisms. To do this, we have studied single crystal Al lines on oxidized silicon.

We have tested lifetimes of passivated and unpassivated Al single crystal lines with various textures. In both passivated and unpassivated lines, the median time to failure, t50, was found to be texture-dependent, with t50(l11) > t50(133) > t50(110), and with t50(111) ∼ 10×t50(110). The activation energy for failure for both passivated and unpassivated (110) single crystal lines was about 1 eV. This value differs from that of aluminum bulk diffusion (1.4 eV), suggesting that interface diffusion is the dominant diffusion mechanism in these lines, and perhaps in bamboo regions of near-bamboo lines as well.

Al-Pd alloys have shown promise for improved IC interconnect manufacturability and reliability. However, there has been little detailed evaluation of microstructure and conductor failure reported for this material. Microstructure and electromigration behaviour of Al-0.35%Pd unpassivated interconnect was studied on films deposited at 250°C or 450°C and patterned into test structures of varying width. Samples were electrically stressed to failure at l×106A/cm2 or 2×106A/cm2. At 450°C, AlPdx precipitates form while at 250°C, palladium remains in solution and a larger grain size is obtained. Slit voids were found in 1μm and 3μm wide lines, though only in the finer lines were the failures transgranular. A very large increase in lifetime of 1μm wide lines with a decrease in current density from 2×106A/cm2 to l×106A/cm2 suggests a critical current effect due to grain boundary clusters in the these lines.

The number of Al triple point junctions (Ntp) correlates inversely to electromigration lifetimes for partially bamboo interconnects that fail by grain boundary (GB) diffusion. This work emphasizes the evolution of statistical microstructural parameters, Ntp and cluster length distribution, during post-pattern anneals. In addition to statistical measures, the structure of specific clusters before and after anneal is compared from TEM images of the same area of the same sample.

Each post-pattern anneal lowers Ntp and shortens the length of individual polycrystalline segments, but with diminishing returns for subsequent anneals. With a TiN capping layer, the statistical microstructural improvement is less but the longest clusters, those most probable as failure sites, lose triple points during anneal. The distribution of cluster lengths is characteristic for a process.

Stress distribution and mass flux in the plane of each grain boundary within a polycrystalline thin-film conductor have been calculated during electromigration for zero flux divergence (steady state) and various boundary conditions. Steady state, representing a balance between the (applied) electric and (induced) stress driving forces, is assumed to develop after a short transient time. Boundary conditions at the intersection of grain boundaries with the top and bottom conductor surfaces (surface junctions) and with the conductor edges (edge junctions) are assumed to be of two types: open (flux passes freely) and closed (zero flux). Flux is assumed to pass freely at the intersection of grain boundaries with each other (triple Junctions). Several grain boundary configurations are considered, including individual boundaries, single triple junctions, and combinations thereof, assuming that bottom surface junctions (conductor/ substrate interface) are closed and that top surface junctions are either open (bare conductor) or closed (passivation layer). Results clearly show the formation of incipient holes and hillocks near the intersection of triple junctions and/or closed (blocked) edge junctions with open surface junctions.

Atomic transport due to electromigration in interconnect lines in integrated circuits depends strongly on temperature. Therefore temperature nonuniformities can create sites of atomic flux divergence resulting in material accumulation or depletion leading to failure. The mechanical stress which will evolve at the sites of material flux divergence will oppose the electromigration driving force. A model is developed to describe the stress evolution during electromigration in the presence of temperature nonuniformnities. Solutions of the differential equations describing the electromigration-induced stress buildup are calculated numerically. The solutions are compared to experimental data in the literature.

An analysis of transition from the electrotransport controlled to the creep controlled electromigration (EM) is made for the Blech test geometry. The analysis rests on the approach developed by the authors with relaxation of electromigration induced stress by diffusional creep and non-linear stress distribution along the line. The derived solution confirms the idea of Glickman and Vilenkin that for high current density as the length of the line decreases the transition from the electrotransport controlled to the creep controlled electromigration kinetics must occur. The value of introduced parameter r that relates electromigration behavior to the creep viscosity is estimated by the comparison with experimental observations for aluminum stripes and discussed in terms of the Coble creep mechanisms.

Electromigration failure in a near bamboo structure is investigated theoretically. Assuming that the diffusion path is interfacial, a flux divergence can be predicted based on the stress gradient induced by grain boundary electromigration in a sub Blech Length grain cluster. A possible explanation for the recently observed “trans-granular” voids is proposed.

Because of the continuing miniaturization, electromigration (EM) phenomena are still a key issue in reliability of VLSI metallizations. The present study of EM induced voiding and hillocking was performed on unpassivated conductor lines with various widths and current densities. Stressed and unstressed interconnects were carefully examined with SEM and TEM techniques, especially with regard to void densities, void sizes and characteristic lengths between void and hillock. The fatal void shape was related to current density and line width indicating that the failure mechanism changes with decreasing line width and decreasing current density.

When a current flows in a conductor, the electron wind causes atoms to diffuse. This paper considers the consequences of such diffusion along dislocation cores. A dislocation climbing in a crystal is viewed as a non-equilibrium thermodynamic system to define the force that drives selfdiffusion along the core. Not only is a dislocation a mass-transport pipe, it also climbs and generates more dislocations—all in the electron wind. A prismatic loop moves like a rigid disk, as atoms electro-migrate along the core from one edge of the loop to the other. Each loop is therefore a mass carrier responding to an electric current. Interstitial and vacancy loops can be simultaneously generated and subsequently climb in the opposite directions. The process transports mass in single crystal or bamboo-like interconnects at moderate temperatures.

A mechanism is proposed to explain electromigration-enhanced precipitate coarsening in Al-Cu alloy interconnects. The interface between the α-phase matrix and a θ-phase Al2Cu precipitate is incoherent, along which both Al and Cu atoms diffuse under an applied electric field. Depending on the relative mobility of Al and Cu, the diffusion causes the precipitate to migrate towards either the positive or the negative electrode. The velocity of a spherical precipitate is proportional to the electric field and the mobilities and inversely proportional to its radius. A critical electric field or precipitate radius exists, above which the precipitate can penetrate a grain boundary. Consequently, the precipitates agglomerate by the synergism between the surface tension-induced ripening and the current-induced migration. The resulting particles are distantly separated, depleting Cu atoms from the rest of the interconnect. The mechanism appears to limit the lifetime of interconnects having bamboo-like grains, tested below 300°C, less than half of the melting temperature of Al.

In this paper an overview of recent developments in understanding electromigration damage mechanisms is given. Based on our detailed studies, both ex-situ and in-situ, of damage in unpassivated near-bamboo lines, we develop a theoretical electromigration damage map. It explains why “slit-like” failure becomes predominant for narrow lines and low current densities. The mechanism of slit formation is discussed in the light of new analytical and numerical simulations of pore shape changes, which take stress effects into account. Possible implications for the rational design of improved metallization alloys are suggested.

Movies showing high voltage scanning electron microscope (HVSEM) in situ observations of void motion in passivated metal lines were produced. By taking pictures of the line when the void morphology changes and combining these images digitally with a technique called morphing, a time-lapse movie is constructed with the minimum amount of stored images. The sequence of still images from which a movie is constructed are shown in this paper. This sequence demonstrates that wedge voids do not cause failure in near-bamboo pure Al lines; rather the void will move until it encounters a grain which it can grow across in a slit-like manner.

An aluminum interconnect can fail by a transgranular slit. We show how a rounded void collapses to such a slit, as atoms diffuse on the void surface, driven by electric current, thermal stress, and surface energy. We use a variational principle to simulate the shape evolution, and identify the critical conditions to trigger the shape instability.

By definition, half of all interconnects fail before the measured mean time to failure (t50) is reached. To predict early failures the basic reactions occurring in the metallization and its environment must be understood. To this end, fatal interconnect failure sites were characterized by Auger electron spectroscopy, atomic force microscopy and backscattered scanning electron microscopy. CVD silicon dioxide passivation layer/fatal void interfaces of typical early failure voids were characterized and compared to a typical late failure void interface. The topographies of these fatal voids were also quantitatively compared to increase our understanding of early failure sites and electromigration.

The study presented in this paper establishes correlations between key passivation morphological characteristics and metal electromigration performance. This was done by using test structures including extrusion monitors which provided narrow gaps along both sides of the test stripes. The parameters studied were: (1) the nature of the gap filling (oxide process and step coverage), (2) local oxide planarization, and (3) oxide thickness above the leads tested. Failure analysis was conducted by SEM cross-sections of cracked passivation areas. We observed that in the case of aluminum metallizations capped by a thin anti-reflective coating (ARC) layer, failure occurred in all cases by aluminum extrusion from the top corners of the leads, and at 45 degree angles into the passivation. Ultimately, the lifetime was dependent on oxide thickness above the test leads rather than gap-filling characteristics.

Electromigration and stress migration are important reliability concerns in the semiconductor industry. Relative and absolute assessments of lifetimes generally rely on the accelerated testing of ‘standard’ test structures. However, the sensitivity to various important electromigration phenomena is found to depend strongly on the type of test structure. Two common structures for electromigration testing are (i) a long line with large pads at either end and (ii) a more realistic interconnect line with W-studs at the line end. The effects of (a) different flux divergences at the line end, (b) interfacial diffusion, and (c) Cu-depletion generally result in different lifetimes for the two types of test structures under the same testing conditions. In this paper, we compare void growth rates and mean times to failure for both types of test structure taking these effects into account. Our results are used to explain differences in MTF values reported in the literature for different test structures.

Electromigration activation energies (Ea) of Al and Cu interconnections are strongly dependent on the grain boundary morphology, and it is pointed out that Ea of bamboo-like Al interconnection is not less than Ea of small grain Cu interconnections. Small resistance oscillatory changes caused by electromigration, which are classified into three categories; oscillation, downward spikes, and upward spikes, are investigated in detail. It seems most likely that oscillations correspond to annihilation and formation of the one void. It is also pointed out that downward spikes are local, while upward spikes are non-local. Dislocation dynamics such as generation, rapid transport and subsequent annihilation are considered to be origins of spikes.

The microstructure of Al alloy integrated circuit conductors strongly affects electromigration failure of the metallization. For submicron linewidths, the microstructure is usually near - bamboo, consisting of alternate polycrystalline and bamboo segments. These polycrystalline segments appear to be much more susceptible to electromigration - induced voiding than the bamboo regions. As a result, microstructural related early failures are a significant concern. In this study we systematically vary line - length to investigate the impact of random microstructural variations on the failure distribution parameters of narrow, multilayer (Ti/TiN/Al/TiN) Al alloy conductors. We show that early failures can occur in 0.6 μm wide stripes. The impact of early void formation on conductor failure, however, is dependent on the resistance failure criterion. By increasing the value, early failures may be eliminated in long line - lengths, suggesting that the resistance failure criterion may provide a means to control the impact of early voiding on the electromigration failure.

Accelerated reliability testing of VLSI layered metallizations involves monitoring the resistance of interconnect test structures under the assumption that changes in the resistance are due to processes (i.e., damage) which are induced by the test conditions (current and/or temperature.) “Failure” of the interconnect is defined as a somewhat arbitrary increase in fractional resistance ΔR/Ro ≈ +10% to +30%, where Ro is the initial resistance. However interpretation of the measured ΔR/Ro (both positive and negative) is complicated by other processes, the test conditions, and the test structure itself which all contribute to ΔR/Ro. We estimate the magnitude of intrinsic factors, such as vacancies and solute effects, as well as extrinsic factors, such as interconnect strain and voiding, on measured on ΔR/Ro. We also show that localized joule heating at voids (a mixed intrinsic + extrinsic effect) principally accounts for the large ΔR/Ro measured during electromigration (i.e., high current) testing. These results suggest improved methods for the detection of interconnect voids induced by the stresses of passivation confinement. We outline the considerations which allow for more rigorous failure criteria which are scalable to any metallization layer scheme, interconnect length and test condition. Finally, we discuss the interpretation of resistance changes at interlevel via structures.