Ion doping technology using a bucket-type ion source to fabricate low temperature poly-Si TFTs is presented. Low energy and high ion density conditions are applied to realize the short doping time and resist mask doping for large area glass substrates. A novel CMOS doping technology with one resist mask process is proposed using compensation and inversion of the shollow doped layer. In combination with excimer laser crystallization and activation below 450°C, high performance CMOS TFTs are produced.

Single crystalline silicon thin films were formed on a transparent quartz substrate by zone melting recrystallization for the application of flat panel display. The recrystallized film shows a perfect (100) texture and the main defects are subgrainboundaries. High residual tensile stress, which can cause the film cracking, can be successfully eliminated by post-annealing. The nchannel thin film transistors fabricated on a recrystallized film showed excellent device characteristics: carrier mobility ˜ 420cm2/Vsec, subthreshold slope ˜ 100mV/dec and off-state leakage current < 0.2pA.

Polysilicon n-type thin film transistors have been fabricated with self-aligned cobalt and nickel silicide contacts to the source and drain regions. The sheet resistance of the source and drain without silicide is above 200 Ω/‪. The cobalt and nickel silicide films have sheet resistance below 30 Ω/‪. The contact resistance of the silicided devices is also much lower. The reduced extrinsic resistance is shown to improve the current in the “on” state, without increasing the leakage current. This study includes examination of cobalt and nickel silicidation on thin polysilicon films at temperatures compatible with polysilicon TFT-LCD processes.

A low temperature process for the oxidation of amorphous and polycrystalline silicon was studied using a helical resonator plasma source. Constant current anodization of amorphous silicon was performed at 350°C and 30 mtorr in an oxygen plasma. Oxidation rate data were analyzed by both parabolic and power law expressions: parabolic rate coefficient B = 23.45 nm2/min and power law rate coefficients α = 0.3807 and C* = 7.3 nm/minα. Oxidation at substrate floating conditions yielded thin oxides; the growth rate saturated after 20 mins, at a thickness of about 10 nm. For TFr fabrication, a two layer oxide was used. The first layer was grown by plasma oxidation to a thickness of about 10 nm to ensure a good interface, and the second layer deposited by PECVD to the final thickness of 35 nm. Electrical properties of control oxides grown on c-Si at the same conditions were promising, with a fixed oxide charge of 1.98 × 1011 charges/cm2 and a mean breakdown field of 5.3 MV/cm after post metallization anneal. The TF's had an average effective electron mobility of 31.1 V/cm2 and an average threshold voltage of 4.6 V.

We have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

A novel defect passivation process of polycrystalline silicon thin-film transistors (poly-Si TFT's) utilizing nitrous oxide (N2O) plasma was investigated. In terms of the gas flow rate, chamber pressure, and plasma exposure time, the optimum plasma condition has been found to significantly improve the electrical characteristics of poly-Si TFTs. The performance is even better than those passivated with conventional hydrogen plasma. It is believed that the nitrogen radicals from the N2O gas as well as the hydrogen ones from the residual H2O both can diffuse into the gate-oxide/poly-Si interface and the channel poly-Si layer to passivate the defect-states. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying N2O-plasma treatment. This novel process is promising for the applications of TFT/liquid crystal displays and TET/static random access memories.

We have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to be critical to enhance the device performance.

A new oxidation process of the poly Silicon thin films has been demonstrated, where the amorphous silicon thin film was oxidized by ECR plasma at room temperature and then crystallized at 600°C for 30hrs(pre-oxidation). For comparison, amorphous silicon thin film was oxidized after crystallization(post-oxidation). The interface roughness turned out to be only 3Å in case of the pre-oxidation process, while the post-oxidation showed about 8Å of the interface roughness. The pre-oxidized TFT showed the constant mobility at high gate voltages, the post-oxidized TFT showed serious degradation of the mobility at high gate voltages.

High performance poly-Si thin film transistors were fabricated by using a new crystallization method, Metal-Induced Lateral Crystallization (MILC). The process temperature was kept below 500°C throughout the fabrication. After the gate definition, thin nickel films were deposited on top of the TFT's without an additional mask, and with a one-step annealing at 500°C, the activation of the dopants in source/drain/gate a-Si films was achieved simultaneously with the crystallization of the a-Si films in the channel area. Even without a post-hydrogenation passivation, mobilities of the MILC TFT's were measured to be as high as 120cm2/Vs and 90cm2/Vs for n-channel and p-channel, respectively. These values are much higher than those of the poly-Si TFT's fabricated by conventional solid-phase crystallization at around 6001C.

Ultrasound treatment (UST) was applied to improve electronic properties of polycrystalline silicon films on silica-based substrates. A strong decrease of sheet resistance by a factor of two orders of magnitude was observed in hydrogenated films at UST temperatures lower than 100°C. This is accompanied by improvement of a film homogeneity as confirmed by spatially resolved photoluminescence study. The UST effect on sheet resistance demonstrates both stable and metastable behavior. A stable UST effect can be accomplished using consecutive cycles of UST and relaxation. An enhanced passivation of grain boundary defects after UST was directly measured by nano-scale contact potential difference with atomic force microscope. Two specific UST processes based on interaction between ultrasound and atomic hydrogen are suggested: enhanced passivation of grain boundary states and UST induced metastability of hydrogen related defects. We also demonstrate a utility of UST for improvement of leakage current and threshold voltage in hydrogenated poly-Si thin film transistors.

An electrically reversible depassivation/passivation phenomenon, recently found for hydrogen passivated polysilicon [1] is further explored in this report. This reversible effect is seen in both ECR and RE hydrogen passivated n-channel thin film transistors (TFTs) but is not seen in the corresponding hydrogen passivated pchannel TFrs, nor is it seen in either n- or p-channel TETs before hydrogenation. This phenomenon has been observed when room temperature bias stressing TFTs fabricated on solid phase or laser crystallized polysilicon films on quartz substrates [1]. A model involving hydrogen release or capture at defects, positively charged hydrogen motion in device electric fields, and subsequent hydrogen capture at other defects has been proposed. This phenomenon has significant implications for polycrystalline silicon TFT’ design and operation. By extension, it also offers significant insight into the stability problems of hydrogenated amorphous silicon.

We present an analytical SPICE model for the AC and DC characteristics of n and p channel polysilicon TFTs which scales fully with channel length and width in all regimes of operation (leakage, subthreshold, above threshold, and kink) and accounts for the frequency dispersion of the capacitance. Once physically based parameters have been extracted from long channel TFTs, which include the gate length and drain bias dependencies of the device parameters, our model accurately reproduces short channel device characteristics. The AC model includes the input channel resistance in series with the gate oxide capacitance. As a result, our model is able to fit the frequency dispersion of the device capacitances. The model has been implemented in the AIM-Spice simulator and good agreement is observed between measured and modeled results for gate lengths down to 4 gim.

Thin-film poly-Si on low-cost substrates is useful for thin-film transistors in flat panel displays or for photovoltaics. The films reported herein were formed at 600°C by d.c. magnetron sputtering from a Si-target onto a SiO2/Mo substrate, pre-coated with Sn or In/Ti to give a liquid phase growth. Poly-Si films have given a preferred (111) orientation, grain size up to 20μm, a carrier mobility exceeding 100cm2/Vs and carrier lifetime of 8μs when using the Sn pre-layer. The Sn pre-layer typically gave smaller grain size than did the In/Ti solvent but the latter gave lower carrier lifetime from Ti incorporation in the film. The film from the Sn pre-layer gave carrier mobility of 140cm2/V-s after hydrogenation by microwave electron cyclotron resonance. Properties of the Si thin-film can be controlled by type of pre-layer, doping of the target, substrate temperature and deposition environment.

Low-temperature crystallization of amorphous Si (a-Si) films was investigated by adsorbing copper ions on the surface of the films. The copper ions were adsorbed by spincoating of Cu solution. This new process lowered the crystallization temperature and reduced crystallization time of a-Si films. For 1000 ppm solution, the a-Si film was partly crystallized down to 500°C in 20 h and almost completely crystallized at 530°C in 20 h. The adsorbed Cu on the surface acted as a seed of crystalline and caused fractal growth. The fractal size was varied from 10 to 200 prm, depending on the Cu concentration in solution. But the grain size of the films was about 400 nm, which was similar to that of intrinsic films crystallized at 600°C.

We have investigated the solid phase crystallization of a-(Si/Si0.7Ge0.3) and a-(Si0.7Ge0.3/Si) bilayer films deposited on SiO2 for an annealing temperature of 550 °C. It was found that, in case of a-(Si0.7Ge0 3/Si), nucleation of crystalline phases occurred at the free surface, while in a-(Si/Si0.7Ge0.3) crystalline phase nucleated at Si0.7Ge0.3/SiO2 interface. The crystallization rate of an a-(Si0.7Ge0.3/Si) is much slower than that of an a-(Si/Si0.7Ge0.3) films. After full crystallization, poly-(Si0.7Ge0.3/Si) has many equiaxed grains and the defect density of the upper Si0.7Ge0.3 was much lower than that of lower Si0.7 Ge0.3 in a poly-(Si/Si0.7Ge0.3) film whose grain morphology was elliptical. The average grain size of poly-(Si0.7Ge0.3/Si) was ˜7 μm and this film had strong (111) preferential orientation, while poly-(Si/Si0.7Ge0.3) had weak (311) or random oriented grains with the average size of˜0.3 μm.

Rapid thermal annealing and furnace annealing for the solid phase crystallization of amorphous silicon thin films deposited using PECVD from argon diluted silane have been compared. Results reveal that the crystallization time, the growth time, and the transient time are temperature activated, and that the resulting polycrystalline silicon grain size is inversely proportional to the annealing temperature, for both furnace annealing and rapid thermal annealing. In addition, rapid thermal annealing was found to result in a lower transient time, a lower growth time, a lower crystallization time, and smaller grain sizes than furnace annealing, for a given annealing temperature. Interestingly, the transient time, growth time, and crystallization time activation energies are much lower for rapid thermal annealing, compared to furnace annealing.

We propose two models to explain the observed differences between rapid thermal annealing and furnace annealing.

The substrate effects on the solid-phase crystallization of amorphous silicon (a-Si) have been extensively investigated. The a-Si films were prepared on two kinds of substrates, a thermally oxidized Si wafer (SiO2/Si) and a quartz, by low-pressure chemical vapor deposition (LPCVD) using Si2H6 gas at 470 °C and annealed at 600 °C in an N2 ambient for crystallization. The analysis using XRD and Raman scattering shows that crystalline nuclei are faster formed on the SiO2/Si than on the quartz, and the time needed for the complete crystallization of a-Si films on the SiO2/Si is greatly reduced to 8 h from ˜15 h on the quartz. In this study, it was first observed that crystallization in the a-Si deposited on the SiO2/Si starts from the interface between the a-Si film and the thermal oxide of the substrate, called interface-induced crystallization, while random nucleation process dominates on the quartz. The very smooth surface of the SiO2/Si substrate is responsible for the observed interface-induced crystallization of a-Si films.

Three approaches to modifying the solid phase crystallization kinetics of amorphous silicon thin films are examined with the goal of reducing the thermal budget and improving the poly-Si quality for thin film transistor applications. The three approaches consist of (1) variations in the PECVD a-Si deposition parameters; (2) the application of pre-fumace-anneal surface treatments; and (3) using both rapid thermal annealing and furnace annealing at different temperatures. We also examine the synergism among these approaches.

Results reveal that (1) film deposition dilution and dilution/temperature changes do not strongly affect crystallization time, but do affect grain size; (2) pre-anneal surface treatments can dramatically reduce the solid phase crystallization thermal budget for diluted films and act synergistically with deposition dilution or dilution/temperature effects; and (3) rapid thermal annealing leads to different crystallization kinetics from that seen for furnace annealing.

Si1−xGex (x≤0.5) films were deposited by using Si2H4 and GeH4 source gases in a low pressure chemical vapor deposition (LPCVD). The deposition temperature was varied from 375 °C for Si0.5Ge0.5 to 450 °C for Si film in order to deposit amorphous Si1−xGex films and the deposition pressure was about 1 Torr. The grain size of polycrystalline Si1−xGex films made by solid phase crystallization (SPC) decreases with germanium content in the films, and the activation energy obtained from the dependence of grain size on annealing temperature was 0.4 eV for Si and 0.45 eV for Si0 69Ge0.31. From obtaining a similar activation energy irrespective of Ge content in the film, the decrease of grain size with germanium content is attributed to the difference of the asdeposited film conditions. The surface roughness of Si1−xGex films investigated by atomic force microscope (AFM) increases with germanium content in the film before and after SPC. For instance, the root-mean square (rms) values of the surface roughness of the as-deposited Si and Si0.5Ge0.5 films were 2.3 and 17 Å, while those values were increased to 2.6 and 41 Å, respectively, after SPC. In order to reduce the surface roughness of Si0.5Ge0.5 film, we have deposited a thin Si capping layer on top of the Si1−xGex layer and identified that this capping layer effectively reduces the increase of surface roughness after SPC.

A simplified technique for characterizing crystallites in polysilicon films has been demonstrated based on use of the atomic force microscope (AFM). The crystallization of films deposited by two different techniques was examined.