Hostname: page-component-78c5997874-lj6df Total loading time: 0 Render date: 2024-11-16T16:10:11.905Z Has data issue: false hasContentIssue false
  • English
  • Français

Wafer Level Modeling of Electrochemical-Mechanical Polishing (ECMP)

Published online by Cambridge University Press:  01 February 2011

Daniel Truque ,
Xiaolin Xie  and
Duane Boning
Daniel Truque
Affiliation:
[email protected], Massachusetts Institute of Technology, Electrical Engineering and Computer Science, 70 Pacific St Apt. 902A, Cambridge, MA, 02139, United States, 7862521268
Xiaolin Xie
Affiliation:
[email protected], Massachusetts Institute of Technology, Microsystems Technology Laboratories, Cambridge, MA, 02139, United States
Duane Boning
Affiliation:
[email protected], Massachusetts Institute of Technology, Microsystems Technology Laboratories, Cambridge, MA, 02139, United States
Get access

Abstract

In this work, we propose a wafer level dynamic ECMP model based on time-evolving current density distributions across the wafer. The copper layer on the wafer surface is discretized, and the potential and current density distributions are calculated based on the applied voltage zones and metal film thicknesses across the wafer. The copper removal rate is proportional to the current density, and thus the copper thickness (and conductance) can be calculated as a function of position on the wafer and polish time. Using a time-stepping simulation, the model is able to capture the wafer level non-uniformity and time-dependence of ECMP removal. The model is also able to capture the time-varying voltage zones used in ECMP, and can be used to find optimal voltage zone control schemes to achieve improved wafer-level uniformity.

Keywords

CMPCuelectrochemical synthesis
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 991: Symposium C – Advances and Challenges in Chemical Mechanical Planarization , 2007 , 0991-C11-04
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1] Chen, L., “Breakthrough technology for CMP”, Semiconductor Fabtech 24th Edition.Google Scholar
[2] Smekalin, K., “Ecmp: Novel Planarization Solution for 65nm and Below”, International Semiconductor Technology Conference Proceeding “Semiconductor Technology” ISTC2005 Applied Materials, Inc. Santa Clara, CA, USA.Google Scholar
[3] Liu, F.Q. et al. , “Cu Planarization in Electrochemical Mechanical Planarization”. Journal of the Electrochemical Society, 153 (6), pp C377–381, 2006.Google Scholar
[4] , Lee, , Brian, “Modeling of Chemical Mechanical Polishing for Shallow Trench Isolation,” Ph.D. Thesis, MIT Dept. of Electrical Engineering and Computer Science, May 2002.Google Scholar
[5] Liu, F.Q. et al. “High Planarization Efficiency and Wide Process Window Using Electro Chemical Mechanical Planarization (EcmpTM)”. Thin Films Group, Applied Materials Inc, Santa Clara, CA, USA.Google Scholar
[6] Brown, A., “Flat, Cheap, and Under Control: Applied Materials' New Polishing Technology Could be the Key to the Coming Generation of Microchips,” IEEE Spectrum, January 2005 Google Scholar
[7] Lu, J., Rogers, C., Manno, V.P., Philiposian, A., Anjur, S., and Moinpur, M.,“Measurements of slurry film thickness and wafer drag during CMP”. Journal of the Electrochemical Society, 151 (4) pp. G241–G247, 2004.Google Scholar