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Valence Band Offset at Amorphous Boron Carbide / Silicon Interfaces

Published online by Cambridge University Press:  23 September 2013

Sean W. King
Affiliation:
Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, U.S.A.
Marc French
Affiliation:
Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, U.S.A.
Milt Jaehnig
Affiliation:
Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, U.S.A.
Markus Kuhn
Affiliation:
Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, U.S.A.
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Abstract

In order to understand the fundamental charge transport in a-B4-5C:H/Si heterostructure devices, we have utilized x-ray photoelectron spectroscopy to determine the valence band offset at interfaces formed by Plasma Enhanced Chemical Vapor Deposition of a-B4-5C:H on (100) Si. For such interfaces, we observed relatively small valence band offset values of ± 0.25 eV.

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Articles
Copyright
Copyright © Materials Research Society 2013 

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